Specifications
Intel
®
Quark Core—Contents
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
4 Order Number: 329679-001US
Contents
1.0 About this Manual.......................................................................................................17
1.1 Manual Contents................................................................................................17
1.2 Notation Conventions.........................................................................................18
1.3 Special Terminology...........................................................................................19
1.4 Related Documents............................................................................................20
2.0 Intel
®
Quark SoC X1000 Core Overview.........................................................................21
2.1 Intel
®
Quark Core Architecture............................................................................21
3.0 Architectural Overview.................................................................................................22
3.1 Internal Architecture ..........................................................................................22
3.2 System Architecture...........................................................................................22
3.3 Memory Organization .........................................................................................22
3.3.1 Address Spaces......................................................................................23
3.3.2 Segment Register Usage..........................................................................24
3.4 I/O Space.........................................................................................................25
3.5 Addressing Modes..............................................................................................25
3.5.1 Addressing Modes Overview.....................................................................25
3.5.2 Register and Immediate Modes.................................................................26
3.5.3 32-Bit Memory Addressing Modes .............................................................26
3.5.4 Differences Between 16- and 32-Bit Addresses ...........................................28
3.6 Data Types .......................................................................................................28
3.6.1 Data Types ............................................................................................28
3.6.1.1 Unsigned Data Types.................................................................29
3.6.1.2 Signed Data Types ....................................................................29
3.6.1.3 BCD Data Types........................................................................30
3.6.1.4 Floating-Point Data Types...........................................................30
3.6.1.5 String Data Types .....................................................................30
3.6.1.6 ASCII Data Types......................................................................31
3.6.1.7 Pointer Data Types....................................................................32
3.6.2 Little Endian vs. Big Endian Data Formats ..................................................33
3.7 Interrupts.........................................................................................................33
3.7.1 Interrupts and Exceptions........................................................................33
3.7.2 Interrupt Processing................................................................................34
3.7.3 Maskable Interrupt..................................................................................34
3.7.4 Non-Maskable Interrupt...........................................................................35
3.7.5 Software Interrupts.................................................................................36
3.7.6 Interrupt and Exception Priorities..............................................................36
3.7.7 Instruction Restart..................................................................................37
3.7.8 Double Fault ..........................................................................................38
3.7.9 Floating-Point Interrupt Vectors................................................................38
4.0 System Register Organization.......................................................................................39
4.1 Register Set Overview........................................................................................39
4.2 Floating-Point Registers......................................................................................39
4.3 Base Architecture Registers.................................................................................39
4.3.1 General Purpose Registers .......................................................................40
4.3.2 Instruction Pointer..................................................................................41
4.3.3 Flags Register ........................................................................................41
4.3.4 Segment Registers..................................................................................44
4.3.5 Segment Descriptor Cache Registers .........................................................44
4.4 System-Level Registers ......................................................................................45
4.4.1 Control Registers....................................................................................46