Specifications

Intel
®
Quark Core—System Register Organization
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
44 Order Number: 329679-001US
IF (INTR Enable Flag, bit 9)
The IF flag, when set, allows recognition of external interrupts signaled on the INTR
pin. When IF is reset, external interrupts signaled on the INTR are not recognized.
IOPL indicates the maximum CPL value allowing alteration of the IF bit when new
values are popped into EFLAGS or FLAGS.
TF (Trap Enable Flag, bit 8)
TF controls the generation of the exception 1 trap when the processor is single-
stepping through code. When TF is set, the Intel
®
Quark SoC X1000 Core
generates an exception 1 trap after the next instruction is executed. When TF is
reset, exception 1 traps occur only as a function of the breakpoint addresses loaded
into debug registers DR[3:0].
SF (Sign Flag, bit 7)
SF is set if the high-order bit of the result is set; otherwise, it is reset. For 8-, 16-,
32-bit operations, SF reflects the state of bits 7, 15, and 31 respectively.
ZF (Zero Flag, bit 6)
ZF is set if all bits of the result are 0; otherwise, it is reset.
AF (Auxiliary Carry Flag, bit 4)
The Auxiliary Flag is used to simplify the addition and subtraction of packed BCD
quantities. AF is set if the operation resulted in a carry out of bit 3 (addition) or a
borrow into bit 3 (subtraction). Otherwise, AF is reset. AF is affected by carry out
of, or borrow into bit 3 only, regardless of overall operand length: 8, 16 or 32 bits.
PF (Parity Flags, bit 2)
PF is set if the low-order eight bits of the operation contain an even number of “1's”
(even parity). PF is reset if the low-order eight bits have odd parity. PF is a function
of only the low-order eight bits, regardless of operand size.
CF (Carry Flag, bit 0)
CF is set if the operation resulted in a carry out of (addition), or a borrow into
(subtraction) the high-order bit. Otherwise, CF is reset. For 8-, 16-, or 32-bit
operations, CF is set according to carry/borrow at bit 7, 15, or 31, respectively.
4.3.4 Segment Registers
Six 16-bit segment registers hold segment selector values identifying the currently
addressable memory segments. In Protected Mode, each segment may range in size
from one byte up to the entire linear and physical address space of the machine, 4
Gbytes (232 bytes). In Real Mode, the maximum segment size is fixed at 64 Kbytes
(216 bytes).
The six addressable segments are defined by the segment registers CS, SS, DS, ES, FS
and GS. The selector in CS indicates the current code segment; the selector in SS
indicates the current stack segment; the selectors in DS, ES, FS, and GS indicate the
current data segments.
4.3.5 Segment Descriptor Cache Registers
The segment descriptor cache registers are not programmer-visible, but it is useful to
understand their content. A programmer-invisible descriptor cache register is
associated with each programmer-visible segment register, as shown in Figure 11. Each
descriptor cache register holds a 32-bit base address, a 32-bit segment limit, and the
other necessary segment attributes.