Specifications

Intel

Quark SoC X1000 Core

October 2013 Developer’s Manual

Order Number: 329679-001US 45

System Register Organization—Intel

Quark Core

Figure 11. Intel

Quark SoC X1000 Core Segment Registers and Associated Descriptor

Cache Registers

When a selector value is loaded into a segment register, the associated descriptor

cache register is automatically updated with the correct information. In Real Mode, only

the base address is updated directly (by shifting the selector value four bits to the left),

because the segment maximum limit and attributes are fixed in Real Mode. In

Protected Mode, the base address, the limit, and the attributes are all updated with the

contents of the segment descriptor indexed by the selector.

When a memory reference occurs, the segment descriptor cache register associated

with the segment being used is automatically involved with the memory reference. The

32-bit segment base address becomes a component of the linear address calculation,

the 32-bit limit is used for the limit-check operation, and the attributes are checked

against the type of memory reference requested.

4.4 System-Level Registers

Figure 12 illustrates the system-level registers, which are the control operation of the

on-chip cache, the on-chip floating-point unit (on the Intel

Quark SoC X1000 Core)

and the segmentation and paging mechanisms. These registers are only accessible to

programs running at privilege level 0, the highest privilege level.

The system-level registers include three control registers and four segmentation base

registers. The three control registers are CR0, CR2 and CR3. CR1 is reserved for future

Intel processors. The four segmentation base registers are the Global Descriptor Table

Table Register (LDTR) and the Task State Segment Register (TR).

A5147-01

———

——

Other Segment Attributes

from Descriptor

Segment LimitPhysical Base Address

GS—

FS—

ES—

DS—

SS—

CS—

Descriptor Registers (Loaded Automatically)

Segment Registers

015

Selector

—