Specifications

Intel
®
Quark Core—System Register Organization
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
46 Order Number: 329679-001US
Figure 12. System-Level Registers
4.4.1 Control Registers
Figure 13 shows the Control Registers which are described in the following sections:
• Section 4.4.1.1, “Control Register 0 (CR0)” on page 47
• Section 4.4.1.2, “Control Register 1 (CR1)” on page 51
• Section 4.4.1.3, “Control Register 2 (CR2)” on page 51
• Section 4.4.1.4, “Control Register 3 (CR3)” on page 51
• Section 4.4.1.5, “Control Register 4 (CR4)” on page 51
A5148-01
CR4
Page Directory Base Register
CR3
Page Fault Linear Address Register
CR2
078151623
24
31
Attributes20-Bit Segment Limit32-Bit Linear Base Address
Descriptor Registers (Loaded Automatically)
System
Segment Registers
015
Selector
Selector
LDTR
TR
Limit32-Bit Linear Base Address
016 15
Selector
Selector
47
IDTR
GDTR
CR0