Specifications

Intel
®
Quark Core—System Register Organization
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
48 Order Number: 329679-001US
The low-order 16 bits of CR0 are also known as the Machine Status Word (MSW). LMSW
and SMSW (load and store MSW) instructions are taken as special aliases of the load
and store CR0 operations, where only the low-order 16 bits of CR0 are involved. The
LMSW and SMSW instructions in the Intel
®
Quark SoC X1000 Core operate only on the
low-order 16 bits of CR0 and ignore the new bits. New Intel
®
Quark SoC X1000 Core
operating systems should use the MOV CR0, Reg instruction.
The defined CR0 bits are described as follows.
PG (Paging Enable, bit 31)
The PG bit is used to indicate whether paging is enabled (PG=1) or disabled
(PG=0). (See Table 10.)
CD (Cache Disable, bit 30)
The CD bit is used to enable the on-chip cache. When CD=1, the cache is not filled
on cache misses. When CD=0, cache fills may be performed on misses. (See
Table 11.)
The state of the CD bit, the cache enable input pin (KEN#), and the relevant page
cache disable (PCD) bit determine whether a line read in response to a cache miss
will be installed in the cache. A line is installed in the cache only when CD=0 and
KEN# and PCD are both zero. The relevant PCD bit comes from either the page
table entry, page directory entry or control register 3. Refer to Section 6.4.7, “Page
Cacheability (PWT and PCD Bits)” on page 103.
CD is set to “1” after RESET.
NW (Not Write-Through, bit 29)
The NW bit enables on-chip cache write-throughs and write-invalidate cycles
(NW=0).
When NW=0, all writes, including cache hits, are sent out to the pins. Invalidate
cycles are enabled when NW=0. During an invalidate cycle, a line is removed from
the cache if the invalidate address hits in the cache. (See Table 11.)
When NW=1, write-throughs and write-invalidate cycles are disabled. A write is not
sent to the pins if the write hits in the cache. With NW=1 the only write cycles that
Table 10. Intel
®
Quark SoC X1000 Core Operating Modes
PG PE Mode
0 0 Real Mode. 32-bit extensions available with prefixes.
01
Protected Mode. 32-bit extensions through both prefixes and “default” prefix setting
associated with code segment descriptors. Also, a sub-mode is defined to support a virtual
8086 processor within the context of the extended processor protection model.
10
Undefined. Loading CR0 with this combination of PG and PE bits causes a GP fault with
error code 0.
11
Paged Protected Mode. All the facilities of Protected Mode, with paging enabled underneath
segmentation.
Table 11. On-Chip Cache Control Modes
CD NW Operating Mode
1 1 Cache fills disabled, write-through and invalidates disabled.
1 0 Cache fills disabled, write-through and invalidates enabled.
0 1 INVALID. If CR0 is loaded with this configuration of bits, a GP fault with error code results.
0 0 Cache fills enabled, write-through and invalidates enabled.