Specifications

Intel

Quark SoC X1000 Core

October 2013 Developer’s Manual

Order Number: 329679-001US 53

System Register Organization—Intel

Quark Core

4.5 Floating-Point Registers

Figure 15 shows the floating-point register set. The on-chip FPU contains eight data

registers, a tag word, a control register, a status register, an instruction pointer and a

data pointer.

4.5.1 Floating-Point Data Registers

Floating-point computations use the Intel

Quark SoC X1000 Core FPU data registers.

These eight 80-bit registers provide the equivalent capacity of twenty 32-bit registers.

Each of the eight data registers is divided into “fields” corresponding to the FPU’s

extended-precision data type.

Figure 15. Floating-Point Registers

The FPU’s register set can be accessed either as a stack, with instructions operating on

the top one or two stack elements, or as a fixed register set, with instructions operating

on explicitly designated registers. The TOP field in the status word identifies the current

top-of-stack register. A “push” operation decrements TOP by one and loads a value into

the new top register. A “pop” operation stores the value from the current top register

and then increments TOP by one. Like other Intel

Quark SoC X1000 Core stacks in

memory, the FPU register stack grows “down” toward lower-addressed registers.

Instructions may address the data registers either implicitly or explicitly. Many

instructions operate on the register at the TOP of the stack. These instructions implicitly

address the register at which TOP points. Other instructions allow the programmer to

explicitly specify which register to use. This explicit register addressing is also relative

to TOP.

A5150-01

Tag Field

Sign Exponent

Significand

047

Instruction Pointer

Data Pointer

015

Control Register

Status Register

Tag Word

64 63 01