Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 57
System Register Organization—Intel
®
Quark Core
Bit 7 is the error summary (ES) status bit. The ES bit is set if any unmasked exception
bit (bits 5:0 in the status word) is set; ES is clear otherwise. The FERR# (floating-point
error) signal is asserted when ES is set.
Bit 6 is the stack flag (SF). This bit is used to distinguish invalid operations due to stack
overflow or underflow. When SF is set, bit 9 (C1) distinguishes between stack overflow
(C1=1) and underflow (C1=0).
Table 18 shows the six exception flags in bits 5:0 of the status word. Bits 5:0 are set to
indicate that the FPU has detected an exception while executing an instruction.
The six exception flags in the status word can be individually masked by mask bits in
the FPU control word. Table 18 lists the exception conditions, and their causes in order
of precedence. Table 18 also shows the action taken by the FPU if the corresponding
exception flag is masked.
An exception that is not masked by the control word causes three things to happen: the
corresponding exception flag in the status word is set, the ES bit in the status word is
set, and the FERR# output signal is asserted. When the Intel
®
Quark SoC X1000 Core
attempts to execute another floating-point or WAIT instruction, exception 16 occurs or
an external interrupt happens if the NE=1 in control register 0. The exception condition
must be resolved via an interrupt service routine. The FPU saves the address of the
floating-point instruction that caused the exception and the address of any memory
operand required by that instruction in the instruction and data pointers. See
Table 16. Condition Code Resulting from Comparison
OrderC3C2C0
TOP > Operand 0 0 0
TOP < Operand 0 0 1
TOP = Operand 1 0 0
Unordered 1 1 1
Table 17. Condition Code Defining Operand Class
C3 C2 C1 C0 Value at TOP
0000+ Unsupported
0001+ NaN
0010- Unsupported
0011- NaN
0100+ Normal
0101+ Infinity
0110- Normal
0111- Infinity
1000+ 0
1001+ Empty
1010- 0
1011- Empty
1 1 0 0 + Denormal
1110- Denormal