Specifications

Intel
®
Quark Core—System Register Organization
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
58 Order Number: 329679-001US
Section 4.5.4.
Note that when a new value is loaded into the status word by the FLDENV (load
environment) or FRSTOR (restore state) instruction, the value of ES (bit 7) and its
reflection in the B bit (bit 15) are not derived from the values loaded from memory. The
values of ES and B are dependent upon the values of the exception flags in the status
word and their corresponding masks in the control word. If ES is set in such a case, the
FERR# output of the Intel
®
Quark SoC X1000 Core is activated immediately.
4.5.4 Instruction and Data Pointers
Because the FPU operates in parallel with the ALU (in the Intel
®
Quark SoC X1000 Core
the arithmetic and logic unit (ALU) consists of the base architecture registers), any
errors detected by the FPU may be reported after the ALU has executed the floating-
point instruction that caused it. To allow identification of the failing numeric instruction,
the Intel
®
Quark SoC X1000 Core contains two pointer registers that supply the
address of the failing numeric instruction and the address of its numeric memory
operand (if appropriate).
The instruction and data pointers are provided for user-written error handlers. These
registers are accessed by the FLDENV (load environment), FSTENV (store
environment), FSAVE (save state) and FRSTOR (restore state) instructions. Whenever
the Intel
®
Quark SoC X1000 Core decodes a new floating-point instruction, it saves the
instruction (including any prefixes that may be present), the address of the operand (if
present) and the opcode.
The instruction and data pointers appear in one of four formats depending on the
operating mode of the Intel
®
Quark SoC X1000 Core (Protected Mode or Real Mode)
and depending on the operand-size attribute in effect (32-bit operand or 16-bit
operand). When the Intel
®
Quark SoC X1000 Core is in the Virtual-86 Mode, the Real
Mode formats are used. Figure 18 through Figure 21 show the four formats. The
floating-point instructions FLDENV, FSTENV, FSAVE and FRSTOR are used to transfer
these values to and from memory. Note that the value of the data pointer is undefined
if the prior floating-point instruction did not have a memory operand.
Note: The operand size attribute is the D bit in a segment descriptor.
Table 18. FPU Exceptions
Exception Cause
Default Action (if
exception is masked)
Invalid
Operation
Operation on a signaling NaN, unsupported format,
indeterminate form (0*∞, 0/0, (+∞) + (-∞), etc.), or stack
overflow/underflow (SF is also set).
Result is a quiet NaN,
integer indefinite, or
BCD indefinite
Denormalized
Operand
At least one of the operands is denormalized; i.e., it has the
smallest exponent but a non-zero significand.
Normal processing
continues
Zero Divisor
The divisor is zero while the dividend is a non-infinite, non-zero
number.
Result is ∞
Overflow
The result is too large in magnitude to fit in the specified
format.
Result is largest finite
value or ∞
Underflow
The true result is non-zero but too small to be represented in
the specified format, and, when underflow exception is
masked, denormalization causes loss of accuracy.
Result is denormalized
or zero
Inexact Result
(Precision)
The true result is not exactly representable in the specified
format (e.g., 1/3); the result is rounded according to the
rounding mode.
Normal processing
continues