Specifications

Intel
®
Quark Core—System Register Organization
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
64 Order Number: 329679-001US
• Do not depend on the ability to retain information written into any reserved bits.
• When loading a register, always load the reserved bits with the values indicated in
the documentation, if any, or reload them with values previously read from the
same register.
Note: Avoid any software dependence upon the state of reserved bits in Intel
®
Quark SoC
X1000 Core registers. Depending upon the values of reserved register bits will make
software dependent upon the unspecified manner in which the processor handles these
bits. Programs that depend upon reserved values risk incompatibility with future
processors.
4.9 Intel
®
Quark Core Model Specific Registers (MSRs)
The following fault conditions are honored when reading/writing to these MSRs:
• #GP(0) is raised if trying to read/write privilege level greater than 0
• #GP(0) is raised if trying to read/write in virtual-8086 mode
• #GP(0) is raised if trying to read/write unimplemented MSR
• #GP(0) is raised if trying to write to reserved bits
When bit 22 of IA32_MISC_ENABLE is set, all CPUID basic leaves above 3 are invisible.
When bit 34 of IA32_MISC_ENABLE is set, CPUID.80000001H:EDX[20] is cleared.
When bit 11 of IA32_EFER is set, XD feature is enabled. However, when bit 34 of
IA32_MISC_ENABLE is set, setting bit 11 of IA32_EFER has no effect.
Table 23. MSRs for Intel
®
Quark Core 1
Name Address Feature Bit definition
IA32_TSC 0x10 Time Stamp Counter
This is a 64-bit counter that increments on
core clock.
IA32_MISC_ENABLE 0x1A0 PAE/XD
[22]=BOOT_NT4
[34]=XD Disable
All other bits are reserved. Writing of 1'b1
to reserved bits causes #GP(0) Fault.
IA32_EFER 0xC000_0080 PAE/XD
[11] - NXE - Execute Disable bit Enable.
All other bits are reserved. Writing of 1'b1
to reserved bits causes #GP(0) Fault.