Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 75
Protected Mode Architecture—Intel
®
Quark Core
Figure 29. System Segment Descriptors
6.2.4.4 LDT Descriptors (S=0, TYPE=2)
LDT descriptors (S=0, TYPE=2) contain information about Local Descriptor Tables. LDTs
contain a table of segment descriptors, unique to a particular task. Because the
instruction to load the LDTR is only available at privilege level 0, the DPL field is
ignored. LDT descriptors are only allowed in the Global Descriptor Table (GDT).
6.2.4.5 TSS Descriptors (S=0, TYPE=1, 3, 9, B)
A Task State Segment (TSS) descriptor contains information about the location, size,
and privilege level of a Task State Segment (TSS). A TSS in turn is a special fixed
format segment that contains all the state information for a task and a linkage field to
permit nesting tasks. The TYPE field is used to indicate whether the task is currently
busy (i.e., on a chain of active tasks) or the TSS is available. The Task Register (TR)
contains the selector that points to the current Task State Segment.
6.2.4.6 Gate Descriptors (S=0, TYPE=4–7, C, F)
Gates are used to control access to entry points within the target code segment. The
various types of gate descriptors are call gates, task gates, interrupt gates, and trap
gates. Gates provide a level of indirection between the source and destination of the
control transfer. This indirection allows the processor to automatically perform
protection checks. It also allows system designers to control entry points to the
operating system. Call gates are used to change privilege levels (see Section 6.3), task
gates are used to perform a task switch, and interrupt and trap gates are used to
specify interrupt service routines.
Figure 30 shows the format of the four types of gate descriptors. Call gates are
primarily used to transfer program control to a more privileged level. The call gate
descriptor consists of three fields: the access byte, a long pointer (selector and offset)
that points to the start of a routine, and a word count that specifies how many
Type Defines Type Defines
0 Invalid 8 Invalid
1 Available 80286 TSS 9
Available Intel
®
Quark SoC X1000
Core TSS
2 LDT A Undefined (Intel Reserved)
3 Busy 80286 TSS B
Busy Intel
®
Quark SoC X1000
Core TSS
4 80286 call gate C
Intel
®
Quark SoC X1000 Core call
gate
5
Task Gate (for 80286, Intel
®
Quark SoC X1000
Core task)
D Undefined (Intel Reserved)
6 80286 interrupt gate E Intel
®
Quark SoC X1000 Core
31 16 0 Byte
Address
0
Segment Base 15...0 Segment Limit 15...0
Base 31...24 G 0 0 0
Limit
19...16
P
DPL
0
Type
Base 23...16
+4