Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 79
Protected Mode Architecture—Intel
®
Quark Core
When operating in Protected Mode, the segment base, limit, and other attributes within
the segment cache registers are defined as shown in Figure 33. In Protected Mode,
each of these fields are defined according to the contents of the segment descriptor
indexed by the selector value loaded into the segment register.
When operating in a Virtual 8086 Mode within the Protected Mode, the segment base,
limit, and other attributes within the segment cache registers are defined as shown in
Figure 34. For compatibility with legacy architecture, the base is set to sixteen times
the current selector value, the limit is fixed at 0000FFFFH, and the attributes are fixed
so as to indicate the segment is present and fully usable. The virtual program executes
at lowest privilege level, level 3, to allow trapping of all IOPL-sensitive instructions and
level-0-only instructions.
Figure 32. Segment Descriptor Caches for Real Address Mode (Segment Limit and
Attributes Are Fixed)
Key:
Y = yes D = expand down
N = no B = byte granularity
0 = privilege level 0 P = page granularity
1 = privilege level 1 W = push/pop 16-bit words
2 = privilege level 2 F = push/pop 32-bit dwords
3 = privilege level 3 – = does not apply to that segment cache register
U = expand up
*Except the 32-bit CS base is initialized to FFFFF000H after reset until first intersegment control transfer (i.e.,
intersegment CALL, or intersegment JMP, or INT). See Figure 34 for an example.