Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 89
Protected Mode Architecture—Intel
®
Quark Core
Each task must have a TSS associated with it. The current TSS is identified by a special
register in the Intel
®
Quark SoC X1000 Core called the Task State Segment Register
(TR). This register contains a selector referring to the task state segment descriptor
that defines the current TSS. A hidden base register and limit register associated with
TR are loaded whenever TR is loaded with a new selector. Returning from a task is
accomplished by the IRET instruction. When IRET is executed, control is returned to the
task that was interrupted. The currently executing task's state is saved in the TSS and
the old task state is restored from its TSS.
Several bits in the flag register and machine status word (CR0) give information about
the state of a task that is useful to the operating system. The Nested Task (NT) (bit 14
in EFLAGS) controls the function of the IRET instruction. If NT = 0, the IRET instruction
performs the regular return; when NT = 1, IRET performs a task switch operation back
to the previous task.
The NT bit is set or reset in the following fashion:
• When a CALL or INT instruction initiates a task switch, the new TSS is marked busy
and the back link field of the new TSS is set to the old TSS selector.
• The NT bit of the new task is set by CALL or INT initiated task switches. An
interrupt that does not cause a task switch clears NT. (The NT bit is restored after
execution of the interrupt handler.) NT may also be set or cleared by POPF or IRET
instructions.
The Intel
®
Quark SoC X1000 Core task state segment is marked busy by changing the
descriptor type field from TYPE 9H to TYPE BH. Use of a selector that references a busy
task state segment causes an exception 13.
The Virtual Mode (VM) bit 17 is used to indicate if a task is a virtual 8086 task. If
VM = 1, the tasks use the Real Mode addressing mechanism. The virtual 8086
environment is entered and exited only via a task switch (see Section 6.5).
The T bit in the Intel
®
Quark SoC X1000 Core TSS indicates that the processor should
generate a debug exception when switching to a task. If T = 1, a debug exception 1 is
generated upon entry to a new task.
6.3.6.1 Floating-Point Task Switching
The FPU's state is not automatically saved when a task switch occurs, because the
incoming task may not use the FPU. The Task Switched (TS) Bit (bit 3 in the CR0) helps
identify the FPU’s state in a multi-tasking environment. Whenever the Intel OverDrive
processors switch tasks, they set the TS bit. The Intel OverDrive processors detect the
first use of a processor extension instruction after a task switch and causes the
processor extension not available exception 7. The exception handler for exception 7
may then decide whether to save the state of the FPU. A processor extension not
present exception (7) occurs when attempting to execute a Floating-Point or WAIT
instruction if the Task Switched and Monitor coprocessor extension bits are both set
(i.e., TS = 1 and MP = 1).
6.3.7 Initialization and Transition to Protected Mode
Because the Intel
®
Quark SoC X1000 Core begins executing in Real Mode immediately
after RESET, it is necessary to initialize the system tables and registers with the
appropriate values.
The GDT and IDT registers must refer to a valid GDT and IDT. The IDT should be at
least 256-bytes long, and GDT must contain descriptors for the initial code and data
segments. Figure 39 shows the tables and Figure 40 shows the descriptors needed for