Specifications
Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 9
Contents—Intel
®
Quark Core
9.6.3 Write-Back Enhanced Intel
®
Quark SoC X1000 Core Pin States During Stop
Grant State ......................................................................................... 176
9.6.4 Clock Control State Diagram.................................................................. 177
9.6.4.1 Normal State.......................................................................... 177
9.6.4.2 Stop Grant State .................................................................... 177
9.6.4.3 Stop Clock State..................................................................... 179
9.6.4.4 Auto HALT Power Down State................................................... 179
9.6.4.5 Stop Clock Snoop State (Cache Invalidations)............................. 179
9.6.4.6 Auto Idle Power Down State..................................................... 180
9.6.5 Write-Back Enhanced Intel
®
Quark SoC X1000 Core Clock Control State
Diagram.............................................................................................. 180
9.6.5.1 Normal State.......................................................................... 180
9.6.5.2 Stop Grant State .................................................................... 181
9.6.5.3 Stop Clock State..................................................................... 182
9.6.5.4 Auto HALT Power Down State................................................... 182
9.6.6 Stop Clock Snoop State (Cache Invalidations) .......................................... 183
9.6.6.1 Auto HALT Power Down Flush State (Cache Flush) for the
Write-Back Enhanced Intel
®
Quark SoC X1000 Core.................... 183
10.0 Bus Operation.......................................................................................................... 184
10.1 Data Transfer Mechanism................................................................................. 184
10.1.1 Memory and I/O Spaces........................................................................ 184
10.1.1.1 Memory and I/O Space Organization ......................................... 185
10.1.2 Dynamic Data Bus Sizing....................................................................... 186
10.1.3 Interfacing with 8-, 16-, and 32-Bit Memories.......................................... 187
10.1.4 Dynamic Bus Sizing during Cache Line Files ............................................. 191
10.1.5 Operand Alignment............................................................................... 192
10.2 Bus Arbitration Logic........................................................................................ 193
10.3 Bus Functional Description................................................................................ 196
10.3.1 Non-Cacheable Non-Burst Single Cycles .................................................. 196
10.3.1.1 No Wait States ....................................................................... 196
10.3.1.2 Inserting Wait States............................................................... 197
10.3.2 Multiple and Burst Cycle Bus Transfers.................................................... 198
10.3.2.1 Burst Cycles........................................................................... 198
10.3.2.2 Terminating Multiple and Burst Cycle Transfers........................... 199
10.3.2.3 Non-Cacheable, Non-Burst, Multiple Cycle Transfers .................... 200
10.3.2.4 Non-Cacheable Burst Cycles..................................................... 200
10.3.3 Cacheable Cycles ................................................................................. 201
10.3.3.1 Byte Enables during a Cache Line Fill......................................... 202
10.3.3.2 Non-Burst Cacheable Cycles..................................................... 202
10.3.3.3 Burst Cacheable Cycles............................................................ 203
10.3.3.4 Effect of Changing KEN# during a Cache Line Fill ........................ 204
10.3.4 Burst Mode Details ............................................................................... 205
10.3.4.1 Adding Wait States to Burst Cycles............................................ 205
10.3.4.2 Burst and Cache Line Fill Order................................................. 206
10.3.4.3 Interrupted Burst Cycles.......................................................... 207
10.3.5 8- and 16-Bit Cycles............................................................................. 209
10.3.6 Locked Cycles...................................................................................... 211
10.3.7 Pseudo-Locked Cycles........................................................................... 212
10.3.7.1 Floating-Point Read and Write Cycles......................................... 213
10.3.8 Invalidate Cycles.................................................................................. 213
10.3.8.1 Rate of Invalidate Cycles ......................................................... 215
10.3.8.2 Running Invalidate Cycles Concurrently with Line Fills.................. 215
10.3.9 Bus Hold............................................................................................. 217
10.3.10Interrupt Acknowledge.......................................................................... 219
10.3.11Special Bus Cycles................................................................................ 220
10.3.11.1HALT Indication Cycle.............................................................. 220