Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 95
Protected Mode Architecture—Intel
®
Quark Core
comprises 512 64-bit entries (PTEs). A PTE is selected using the physical address
defined as follows:
— Bits 31:12 are from the PDE.
— Bits 11:3 are bits 20:12 of the linear address.
— Bits 2:0 are 0.
• Because a PTE is identified using bits 31:12 of the linear address, every PTE maps
a 4-KByte page (see Table 33). The final physical address is computed as follows:
— Bits 31:12 are from the PTE.
— Bits 11:0 are from the original linear address.
If the P flag (bit 0) of a PDE or a PTE is 0 or if a PDE or a PTE sets any reserved bit, the
entry is used neither to reference another paging-structure entry nor to map a page. A
reference using a linear address whose translation would use such a paging structure
entry causes a page-fault exception.
The following bits are reserved with PAE paging:
• If the P flag (bit 0) of a PDE or a PTE is 1, bits 62:MAXPHYADDR are reserved.
• If the P flag and the PS flag (bit 7) of a PDE are both 1, bits 20:13 are reserved.
• If IA32_EFER.NXE = 0 and the P flag of a PDE or a PTE is 1, the XD flag (bit 63) is
reserved.
• If the PAT is not supported (as in Intel
®
Quark SoC X1000 Core):
— If the P flag of a PTE is 1, bit 7 is reserved.
— If the P flag and the PS flag of a PDE are both 1, bit 12 is reserved.
A reference using a linear address that is successfully translated to a physical address
is performed only if allowed by the access rights of the translation.
Figure 41. Linear-Address Translation to a 4-KByte Page using PAE Paging