Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 103
Protected Mode Architecture—Intel
®
Quark Core
The R/W and U/S bits provide protection from user access on a page-by-page basis
because the bits are contained in the page table entry and the page directory table.
The U/S and R/W bits in the first-level page directory table apply to all entries in the
page table pointed to by that directory entry. The U/S and R/W bits in the second-level
page table entry apply only to the page described by that entry. The most restrictive
U/S and R/W bits from the page directory table and the page table entry are used to
address a page.
Example: If the U/S and R/W bits for the page directory entry were 10 (user
read/execute) and the U/S and R/W bits for the page table entry were 01 (no user
access at all), the access rights for the page would be 01, the numerically smaller of
the two.
Note: A given segment can be easily made read-only for level 0, 1, or 2 via use of segmented
protection mechanisms.
6.4.7 Page Cacheability (PWT and PCD Bits)
See Section 7.6, “Page Cacheability” on page 119 for a detailed description of page
cacheability and the PWT and PCD bits.
6.4.8 Translation Lookaside Buffer
The Intel
®
Quark SoC X1000 Core paging hardware is designed to support demand
paged virtual memory systems. However, performance would degrade substantially if
the Intel
®
Quark SoC X1000 Core were required to access two levels of tables for every
memory reference. To solve this problem, the Intel
®
Quark SoC X1000 Core keeps a
cache of the most recently accessed pages. This cache is called the Translation
Lookaside Buffer (TLB). The TLB is a four-way set associative 32-entry page table
cache. It automatically keeps the most commonly used page table entries in the Intel
®
Quark SoC X1000 Core. The 32-entry TLB coupled with a 4 Kbyte page size, results in
coverage of 128 Kbytes of memory addresses.
Figure 45 illustrates how the TLB complements the Intel
®
Quark SoC X1000 Core's
paging mechanism.
Table 34. Page Level Protection Attributes
U/S R/W WP User Access Supervisor Access
0 0 0 None Read/Write/Execute
0 1 0 None Read/Write/Execute
1 0 0 Read/Execute Read/Write/Execute
1 1 0 Read/Write/Execute Read/Write/Execute
0 0 1 None Read/Execute
0 1 1 None Read/Write/Execute
1 0 1 Read/Execute Read/Execute
1 1 1 Read/Write/Execute Read/Write/Execute