Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 107
Protected Mode Architecture—Intel
®
Quark Core
Note: Even though the bits in the error code (U/S, W/R, and P) have similar names as the bits
in the Page Directory/Table Entries, the interpretation of the error code bits is different.
Figure 47 indicates what type of access caused the page fault.
6.4.11 Operating System Responsibilities
The Intel
®
Quark SoC X1000 Core takes care of the page address translation process,
relieving the burden from an operating system in a demand-paged system. The
operating system is responsible for setting up the initial page tables, and handling any
page faults. The operating system also is required to invalidate (i.e., flush) the TLB
when any changes are made to any of the page table entries. The operating system
must reload CR3 to cause the TLB to be flushed.
Setting up the tables requires loading CR3 with the address of the page directory, and
allocating space for the page directory and the page tables. The primary responsibilities
of the operating system are to implement a swapping policy and handle all of the page
faults.
The operating system must ensure that the TLB cache matches the information in the
paging tables. In particular, when the operating system sets the P bit of page table
entry to zero, the TLB must be flushed. Operating systems may want to take advantage
of the fact that CR3 is stored as part of a TSS, to give every task or group of tasks its
own set of page tables.
6.5 Virtual 8086 Environment
6.5.1 Executing Programs
The Intel
®
Quark SoC X1000 Core allows the execution of application programs in both
Real Mode and in the Virtual 8086 Mode (Virtual Mode). Of the two methods, Virtual
8086 Mode offers the system designer the most flexibility. The Virtual 8086 Mode
allows the execution of applications while still allowing the system designer to take full
advantage of the Intel
®
Quark SoC X1000 Core protection mechanism. Figure 48
illustrates this concept.
Figure 47. Page Fault System Information
15 3210
UUUUUUUUUUUUUUSWRP
U/S W/R Access Type
00Supervisor† Read
01Supervisor Write
10User Read
11User Write
†Descriptor table access faults with U/S = 0, even if the program is executing at level 3.
Key
•U: UNDEFINED
• U/S: The U/S bit indicates whether the access causing the fault occurred when the Intel
®
Quark
SoC X1000 Core was executing in User Mode (U/S = 1) or in Supervisor mode (U/S = 0).
• W/R: The W/R bit indicates whether the access causing the fault was a Read (W/R = 0) or a
Write (W/R = 1).
• P: The P bit indicates whether a page fault was caused by a not-present page (P = 0), or by a
page level protection violation (P = 1).