Specifications

Intel
®
Quark Core—On-Chip Cache
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
114 Order Number: 329679-001US
7.0 On-Chip Cache
The Intel
®
Quark SoC X1000 Core processor has a 16-Kbyte cache, as discussed in
Section 7.1.1. The cache is software-transparent to maintain binary compatibility with
previous generations of the Intel Architecture.
The on-chip cache is designed for maximum flexibility and performance. The cache has
several operating modes, offering flexibility during program execution and debugging.
Memory areas can be defined as non-cacheable by software and external hardware.
Protocols for cache line invalidations and cache replacement are implemented in
hardware, easing system design.
7.1 Cache Organization
The on-chip cache is a unified code and data cache; that is, the cache is used for both
instruction and data accesses and acts on physical addresses.
The cache organization is 4-way set associative and each line is 16 bytes wide. The 16
Kbytes of cache memory are logically organized as 256 sets, each containing four lines.
The cache memory is physically split into four 4-Kbyte blocks, each containing 256 lines
(see Figure 50). There are 256 21-bit tags associated with each 4-Kbyte block. There is
a valid bit for each line in the cache. Each line in the cache is either valid or not valid;
there are no provisions for partially valid lines.
Figure 50. On-Chip Cache Physical Organization
20-Bit
Tag
16-Byte
Line Size
4K Bytes
256
Sets
256
Tags
4K Bytes
4K Bytes
4K Bytes
4 Valid
Bits
3 LRU
Bits
256
Sets