Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 117
On-Chip Cache—Intel
®
Quark Core
CD=1, NW=1
The 1,1 state is best used when no lines are allocated, which occurs naturally after
RESET (but not SRESET), but must be forced (e.g., by the WBINVD instruction)
when entered during normal operation. In these cases, the Write-Back Enhanced
Intel
®
Quark SoC X1000 Core operates as if it had no cache at all.
When the 1,1 state is exited, lines that are allocated as write-back are written back
upon a snoop hit or replacement cycle. Lines that were allocated as write-through
(and later modified while in the 1,1 state) never appear on the bus.
CD=1, NW=0
The only difference between this state and the normal 0,0 “run” state is that new
line fills (and the line replacements that result from capacity limitations) do not
occur. This causes the contents of the cache to be locked in, unless lines are
invalidated using snoops.
7.3 Cache Line Fills
Any area of memory can be cached in the Intel
®
Quark SoC X1000 Core. Non-
cacheable portions of memory can be defined by the external system or by software.
The external system can inform the Intel
®
Quark SoC X1000 Core that a memory
address is non-cacheable by returning the KEN# pin inactive during a memory access.
(Refer to Section 10.3.3, “Cacheable Cycles” on page 201.) Software can prevent
certain pages from being cached by setting the PCD bit in the page table entry.
A read request can be generated from program operation or by an instruction pre-
fetch. The data is supplied from the on-chip cache when a cache hit occurs on the read
address. When the address is not in the cache, a read request for the data is generated
on the external bus.
When the read request is to a cacheable portion of memory, the Intel
®
Quark SoC
X1000 Core initiates a cache line fill. During a line fill a 16-byte line is read into the
Intel
®
Quark SoC X1000 Core. Cache line fills are generated only for read misses. Write
misses never cause a line in the internal cache to be allocated. When a cache hit occurs
on a write, the line is updated. Cache line fills can be performed over 8- and 16-bit
buses using the dynamic bus sizing feature. Refer to Section 10.1.2, “Dynamic Data
Bus Sizing” on page 186 and Section 10.3.3, “Cacheable Cycles” on page 201 for
further information.
Table 37. Write-Back Enhanced Intel
®
Quark SoC X1000 Core Write-Back Cache
Operating Modes
CR0, CD, NW Read Hit Read Miss
WRITE HIT
(See Note)
Write
Miss
Snoops
1,1
(state after reset)
read cache read bus (no fill)
write cache
(no write-through)
write bus
not
accepted
1,0 read cache read bus (no fill) write cache, write bus if S write bus
normal
operation
0,1
This is a fault-protected disallowed state. A GP(0) occurs when an attempt is made to
load CR0 with this state.
0,0
(state DURING
normal operation)
read cache read bus, line fill write cache, write bus if S write bus
normal
operation
Note: Normal MESI state transitions occur on write hits in all legal states.