Specifications

Intel
®
Quark Core—On-Chip Cache
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
118 Order Number: 329679-001US
7.4 Cache Line Invalidations
The Intel
®
Quark SoC X1000 Core contains both a hardware and software mechanism
for invalidating internal cache lines. Cache line invalidations are needed to keep the
cache contents consistent with external memory. Refer to Section 10.3.8, “Invalidate
Cycles” on page 213 for further information.
7.4.1 Write-Back Enhanced Intel
®
Quark SoC X1000 Core Snoop
Cycles and Write-Back Mode Invalidation
In Enhanced Bus Mode, the Write-Back Enhanced Intel
®
Quark SoC X1000 Core
performs invalidations differently. Snoop cycles are initiated by the system to
determine whether a line is present in the cache, and what the state is. Snoop cycles
may be classified further as Inquire cycles or Invalidate cycles. When another bus
master initiates a memory read cycle, inquire cycles are driven to the Write-Back
Enhanced Intel
®
Quark SoC X1000 Core to determine whether the processor cache
contains the latest data. When the snooped line is in the Write-Back Enhanced Intel
®
Quark SoC X1000 Core’s cache and the line contains the most recent information, the
processor must schedule a write back of the data. Inquire cycles are driven with INV =
‘0’. Invalidate cycles are driven to the Write-Back Enhanced Intel
®
Quark SoC X1000
Core when the other bus master initiates a memory write cycle to determine whether
the Write-Back Enhanced Intel
®
Quark SoC X1000 Core cache contains the snooped
line. The invalidate cycles are driven with INV = ‘1’, so that when the snooped line is in
the on-chip cache, the line is invalidated. Snoop cycles are described in detail in Section
10.3, “Bus Functional Description” on page 196.
The Write-Back Enhanced Intel
®
Quark SoC X1000 Core has control mechanisms
(including snooping) for writing back the modified lines and invalidating the cache.
There are special bus cycles associated with write-backs and with invalidation. All of the
Write-Back Enhanced Intel
®
Quark SoC X1000 Core’s special cycles require
acknowledgment by RDY# or BRDY#. During the special cycles, the addresses shown in
Table 38 are driven onto the address bus and the data bus is left undefined.
7.5 Cache Replacement
Before a line is placed in its internal cache, the Intel
®
Quark SoC X1000 Core checks
whether there is a non-valid line in the set; that line is replaced first. When all four
lines in the set are valid, a pseudo least-recently-used mechanism is used to determine
which line should be replaced.
A valid bit is associated with each line in the cache. Before a line is placed in a set, the
four valid bits are checked to see whether there is a non-valid line that can be replaced.
When a non-valid line is found, that line is marked for replacement.
The four lines in the set are labeled l0, l1, l2, and l3. The order in which the valid bits
are checked during an invalidation is l0, l1, l2 and l3. All valid bits are cleared when the
processor is reset or when the cache is flushed.