Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 119
On-Chip Cache—Intel
®
Quark Core
The pseudo LRU mechanism works in the following manner: When a line must be
replaced, the cache first selects which of lines 11:10 and 13:12 was least recently
used. Then the cache determines which of the two lines was least recently used and
mark it for replacement. This decision tree is shown in Figure 51.
Figure 51. On-Chip Cache Replacement Strategy
7.6 Page Cacheability
Two bits for cache control, PWT and PCD, are defined in the page table and page
directory entries. The states of these bits are driven out on the PWT and PCD pins
during memory access cycles.
The PWT bit controls the write policy for second-level caches used with the Intel
®
Quark SoC X1000 Core. Setting PWT=1 defines a write-through policy for the current
page while PWT=0 defines the possibility of write-back. The state of PWT is ignored
internally by the Intel
®
Quark SoC X1000 Core for on-chip cache in write through
mode.
The PCD bit controls cacheability on a page-by-page basis. The PCD bit is internally
AND’ed with the KEN# signal to control cacheability on a cycle-by-cycle basis (see
Figure 52). PCD=0 enables caching while PCD=1 forbids it. Note that cache fills are
enabled when PCD=0 AND KEN#=0. This logical AND is implemented physically with a
NOR gate.
Table 38. Encoding of the Special Cycles for Write-Back Cache
Cycle Name M/IO# D/C# W/R# BE[3:0]# A[4:2]
Write-Back
†
0 0 1 0111 000
First Flush Ack Cycle
†
0 0 1 0111 001
Flush
†
0 0 1 1101 000
Second Flush Ack Cycle
†
0 0 1 1101 001
Shutdown 0 0 1 1110 000
HALT 0 0 1 1011 000
Stop Grant Ack Cycle 0 0 1 1011 100
† Write-Back Enhanced Intel
®
Quark SoC X1000 Core only. FLUSH differs for Standard Mode.
All four lines
in the set valid?
No
Yes
B0 = 0?
Yes: I0 or I1
least recently used
No: I2 or I3
least recently used
B1 = 0?
B2 = 0?
Yes
No
Yes
No
Replace
I0
Replace
I1
Replace
I2
Replace
I3
Replace
non-valid line