Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 129
System Management Mode (SMM) Architectures—Intel
®
Quark Core
The System Management Interrupt hardware interface consists of the SMI# interrupt
request input and the SMIACT# output the system uses to decode the SMRAM.
Figure 54. Basic SMI# Hardware Interface
8.3.1 System Management Interrupt (SMI#)
SMI# is a falling-edge triggered, non-maskable interrupt request signal. SMI# is an
asynchronous signal, but setup and hold times t
20
and t
21
must be met in order to
guarantee recognition on a specific clock. The SMI# input need not remain active until
the interrupt is actually serviced. The SMI# input must remain active for a single clock
if the required setup and hold times are met. SMI# also works correctly if it is held
active for an arbitrary number of clocks.
The SMI# input must be held inactive for at least four external clocks after it is
asserted to reset the edge triggered logic. A subsequent SMI# might not be recognized
if the SMI# input is not held inactive for at least four clocks after being asserted.
SMI#, like NMI, is not affected by the IF bit in the EFLAGS register and is recognized on
an instruction boundary. An SMI# does not break locked bus cycles. The SMI# has a
higher priority than NMI and is not masked during an NMI. In order for SMI# to be
recognized with respect to SRESET, SMI# should not be asserted until two (2) clocks
after SRESET becomes inactive.
After the SMI# interrupt is recognized, the SMI# signal is masked internally until the
RSM instruction is executed and the interrupt service routine is complete. Masking the
SMI# prevents recursive SMI# calls. SMI# must be deasserted for at least four clocks
to reset the edge triggered logic. If another SMI# occurs while the SMI# is masked, the
pending SMI# is recognized and executed on the next instruction boundary after the
current SMI# completes. This instruction boundary occurs before execution of the next
instruction in the interrupted application code, resulting in back-to-back SMM handlers.
Only one SMI# can be pending while SMI# is masked.
The SMI# signal is synchronized internally and must be asserted at least three CLK
periods prior to asserting the RDY# signal in order to guarantee recognition on a
specific instruction boundary. This is important for servicing an I/O trap with an SMI#
handler (see Figure 55).
8.3.2 SMI# Active (SMIACT#)
SMIACT# indicates that the processor is operating in System Management Mode. The
processor asserts SMIACT# in response to an SMI# interrupt request on the SMI# pin.
SMIACT# is driven active after the processor has completed all pending write cycles
(including emptying the write buffers), and before the first access to SMRAM, when the
processor saves (writes) its state (or context) to SMRAM. SMIACT# remains active until
the last access to SMRAM when the processor restores (reads) its state from SMRAM.
SMIACT# does not float in response to HOLD. SMIACT# is used by the system logic to
decode SMRAM (see Figure 56).
CPU
}
SMI Interface