Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 13
Contents—Intel
®
Quark Core
61 I/O Instruction Restart............................................................................................ 139
62 SMM Base Location ................................................................................................ 140
63 SMRAM Usage ....................................................................................................... 141
64 SMRAM Location .................................................................................................... 142
65 FLUSH# Mechanism during SMM.............................................................................. 143
66 Cached SMM ......................................................................................................... 143
67 Non-Cached SMM................................................................................................... 144
68 Write-Back Enhanced Intel
®
Quark SoC X1000 Core Cache Flushing for Overlaid
SMRAM upon Entry and Exit of Cached SMM .............................................................. 145
69 Functional Signal Groupings .................................................................................... 150
70 Reordering of a Reads with Write Buffers................................................................... 168
71 Reordering of a Reads with Write Buffers................................................................... 168
72 Pin States During RESET......................................................................................... 172
73 Stop Clock Protocol ................................................................................................ 175
74 Intel
®
Quark SoC X1000 Core Stop Clock State Machine ............................................. 178
75 Recognition of Inputs when Exiting Stop Grant State .................................................. 179
76 Write-Back Enhanced Intel
®
Quark SoC X1000 Core Stop Clock State Machine
(Enhanced
Bus Configuration) ................................................................................................. 181
77 Physical Memory and I/O Spaces.............................................................................. 185
78 Physical Memory and I/O Space Organization............................................................. 186
79 Intel
®
Quark SoC X1000 Core with 32-Bit Memory ..................................................... 188
80 Addressing 16- and 8-Bit Memories.......................................................................... 188
81 Logic to Generate A1, BHE# and BLE# for 16-Bit Buses .............................................. 190
82 Data Bus Interface to 16- and 8-Bit Memories............................................................ 191
83 Single Master Intel
®
Quark Core System................................................................... 193
84 Single Intel
®
Quark Core with DMA .......................................................................... 194
85 Single Intel
®
Quark Core with Multiple Secondary Masters........................................... 195
86 Basic 2-2 Bus Cycle................................................................................................ 197
87 Basic 3-3 Bus Cycle................................................................................................ 198
88 Non-Cacheable, Non-Burst, Multiple-Cycle Transfers................................................... 200
89 Non-Cacheable Burst Cycle...................................................................................... 201
90 Non-Burst, Cacheable Cycles ................................................................................... 203
91 Burst Cacheable Cycle ............................................................................................ 204
92 Effect of Changing KEN#......................................................................................... 205
93 Slow Burst Cycle.................................................................................................... 206
94 Burst Cycle Showing Order of Addresses ................................................................... 207
95 Interrupted Burst Cycle........................................................................................... 208
96 Interrupted Burst Cycle with Non-Obvious Order of Addresses...................................... 209
97 8-Bit Bus Size Cycle ............................................................................................... 210
98 Burst Write as a Result of BS8# or BS16#................................................................. 211
99 Locked Bus Cycle................................................................................................... 212
100 Pseudo Lock Timing................................................................................................ 213
101 Fast Internal Cache Invalidation Cycle ...................................................................... 214
102 Typical Internal Cache Invalidation Cycle................................................................... 214
103 System with Second-Level Cache ............................................................................. 216
104 Cache Invalidation Cycle Concurrent with Line Fill....................................................... 217
105 HOLD/HLDA Cycles................................................................................................. 218
106 HOLD Request Acknowledged during BOFF#.............................................................. 219
107 Interrupt Acknowledge Cycles.................................................................................. 220
108 Stop Grant Bus Cycle.............................................................................................. 221
109 Restarted Read Cycle.............................................................................................. 222
110 Restarted Write Cycle............................................................................................. 223
111 Bus State Diagram................................................................................................. 224
112 Basic Burst Read Cycle ........................................................................................... 227