Specifications

Intel
®
Quark Core—System Management Mode (SMM) Architectures
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
130 Order Number: 329679-001US
The number of CLKs required to complete the SMM state save and restore is dependent
on-system memory performance. The values listed in Table 42 assume zero wait-state
memory writes (two CLK cycles), 2-1-1-1 burst read cycles, and zero wait-state non-
burst reads (2 CLK cycles). Additionally, it is assumed that the data read during the
SMM state restore sequence is not cacheable.
Figure 55. SMI# Timing for Servicing an I/O Trap
Figure 56 can be used for latency calculations.
Figure 56. Intel
®
Quark SoC X1000 Core SMIACT# Timing
8.3.3 SMRAM
The Intel
®
Quark SoC X1000 Core uses the SMRAM space for state save and state
restore operations during an SMI# and RSM. The SMI# handler, which also resides in
SMRAM, uses the SMRAM space to store code, data and stacks. In addition, the SMI#
handler can use the SMRAM for system management information such as the system
configuration, configuration of a powered-down device, and system design-specific
information.
CLK
SMI#
BRDY#
t
nd
t
su
A5232-01
SMI#
Sampled
A
Note: Setup time (A) for recognition on I/O instruction boundary.
CLK
ADS#
SMI#
SMIACT#
BRDY#
A5233-01
A
E F
B
C
D
G
Normal StateSystem Management ModeNormal State
Normal
State
State
Restore
SIMM
Handler
State
Save
T2T1