Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 131
System Management Mode (SMM) Architectures—Intel
®
Quark Core
The processor asserts the SMIACT# output to indicate to the memory controller that it
is operating in System Management Mode. The system logic should ensure that only
the processor has access to this area. Alternate bus masters or DMA devices that try to
access the SMRAM space when SMIACT# is active should be directed to system RAM in
the respective area.
The system logic is minimally required to decode the physical memory address range
from 38000H-3FFFFH as SMRAM area. The processor saves its state to the state save
area from 3FFFFH downward to 3FE00H. After saving its state the processor jumps to
the address location 38000H to begin executing the SMI# handler. The system logic
can choose to decode a larger area of SMRAM as needed. The size of this SMRAM can
be between 32 Kbytes and 4 Gbytes.
The system logic should provide a manual method for switching the SMRAM into
system memory space when the processor is not in SMM. This enables initialization of
the SMRAM space (i.e., loading SMI# handler) before executing the SMI# handler
during SMM (see Figure 57).
8.3.3.1 SMRAM State Save Map
When the SMI# is recognized on an instruction boundary, the processor core first sets
SMIACT# low, indicating to the system logic that accesses are now being made to the
system-defined SMRAM areas. The processor then writes its state to the state save
area in the SMRAM. The state save area starts at CS Base + [8000H + 7FFFH]. The
default CS Base is 30000H; therefore the default state save area is at 3FFFFH. In this
case, the CS Base can also be referred to as the SMBASE.
If SMBASE relocation is enabled, then the SMRAM addresses can change. The following
formula is used to determine the relocated addresses where the context is saved. The
context resides at CS Base + [8000H + Register Offset], where the default initial CS
Base is 30000H and the Register Offset is listed in the SMRAM state save map
(Table 42). Reserved spaces are used to accommodate new registers in future
processors. The state save area starts at 7FFFH and continues downward in a stack-like
fashion.
Some of the registers in the SMRAM state save area may be read and changed by the
SMI# handler, with the changed values restored to the processor registers by the RSM
instruction. Some register images are read-only, and must not be modified (modifying
these registers results in unpredictable behavior). The values stored in reserved areas
may change in future processors. An SMM handler should not rely on any values stored
in a reserved area.