Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 133
System Management Mode (SMM) Architectures—Intel
®
Quark Core
8.3.4 Exit From SMM
The RSM instruction is only available to the SMI# handler. The opcode of the instruction
is 0FAAH. Execution of this instruction while the processor is executing outside of SMM
causes an invalid opcode error. The last instruction of the SMI# handler is the RSM
instruction.
The RSM instruction restores the state save image from SMRAM back to the processor,
then returns control back to the interrupted program execution. There are three SMM
features that can be enabled by writing to control “slots” in the SMRAM state save area.
7FE0 ESP YES
7FDC EBX YES
7FD8 EDX YES
7FD4 ECX YES
7FD0 EAX YES
7FCC DR6 NO
7FC8 DR7 NO
7FC4 TR
1
NO
7FC0 LDTR
1
NO
7FBC GS
1
NO
7FB8 FS
1
NO
7FB4 DS
1
NO
7FB0 SS
1
NO
7FAC CS
1
NO
7FA8 ES
1
NO
7FA7–7F98 Reserved NO
7F94 IDT Base NO
7F93–7F8C Reserved NO
7F88 GDT Base NO
7F87-7F04 Reserved NO
7F02 Auto HALT Restart Slot (Word)
3
YES
7F00 I/O Trap Restart Slot (Word)
3
YES
7EFC SMM Revision Identifier (Dword)
3
NO
7EF8 SMBASE Slot (Dword)
3
YES
7EF7–7E00 Reserved NO
Table 42. SMRAM State Save Map (Sheet 2 of 2)
Register Offset Register Writeable?
2
Notes:
1. Upper two bytes are reserved.
2. Modifying a value that is marked as not writeable results in
unpredictable behavior.
3. Words are stored in two consecutive bytes in memory with
the low-order byte at the lowest address and the high-order
byte at the high address.