Specifications

Intel
®
Quark Core—System Management Mode (SMM) Architectures
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
136 Order Number: 329679-001US
When the processor invokes SMM, the processor core registers are initialized as shown
in Table 43.
The following is a summary of the key features in the SMM environment:
1. Real Mode style address calculation.
2. 4-Gbyte limit checking.
3. IF flag is cleared.
4. NMI is disabled.
5. TF flag in EFLAGS is cleared; single step traps are disabled.
6. DR7 is cleared, except for bits 12 and 13; debug traps are disabled.
7. The RSM instruction no longer generates an invalid opcode error.
8. Default 16-bit opcode, register and stack use.
All bus arbitration (HOLD, AHOLD, BOFF#) inputs and bus sizing (BS8#, BS16#) inputs
operate normally while the processor is in SMM.
8.4.2.1 Write-Back Enhanced Intel
®
Quark SoC X1000 Core Environment
When the Write-Back Enhanced Intel
®
Quark SoC X1000 Core is in Enhanced Bus
Mode, SMI# has greater priority than debug exceptions and external interrupts, except
for FLUSH# and SRESET (see Section 3.7.6).
8.4.3 Executing System Management Mode Handler
The processor begins execution of the SMM handler at offset 8000H in the CS segment.
The CS Base is initially 30000H. However, the CS Base can be changed by using the
SMM Base relocation feature.
When the SMM handler is invoked, the processors PE and PG bits in CR0 are reset to 0.
The processor is in an environment similar to Real mode, but without the 64-Kbyte limit
checking. However, the default operand size and the default address size are set to 16
bits.
Table 43. SMM Initial Processor Core Register Settings
Register Contents
General Purpose Registers Unpredictable
EFLAGS 00000002H
EIP 00008000H
CS Selector 3000H
CS Base
SMM Base
(default 30000H)
DS, ES, FS, GS, SS
Selectors
0000H
DS, ES, FS, GS, SS Bases 000000000H
DS, ES, FS, GS, SS Limits 0FFFFFFFFH
CR0
Bits 0,2,3 & 31 cleared
(PE, EM, TS & PG); others
are unmodified
DR6 Unpredictable
DR7 00000000H