Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 137
System Management Mode (SMM) Architectures—Intel
®
Quark Core
The EM bit is cleared so that no exceptions are generated. (If the SMM was entered
from Protected Mode, the Real Mode interrupt and exception support is not available.)
The SMI# handler should not use floating-point unit instructions until the FPU is
properly detected (within the SMI# handler) and the exception support is initialized.
Because the segment bases (other than CS) are cleared to 0 and the segment limits
are set to 4 Gbytes, the address space may be treated as a single flat 4-Gbyte linear
space that is unsegmented. The processor is still in Real Mode and when a segment
selector is loaded with a 16-bit value, that value is then shifted left by 4 bits and loaded
into the segment base cache. The limits and attributes are not modified.
In SMM, the processor can access or jump anywhere within the 4-Gbyte logical address
space. The processor can also indirectly access or perform a near jump anywhere
within the 4-Gbyte logical address space.
8.4.3.1 Exceptions and Interrupts within System Management Mode
When the processor enters SMM, it disables INTR interrupts, debug and single-step
traps by clearing the EFLAGS, DR6 and DR7 registers. This prevents a debug
application from accidentally breaking into an SMM handler. This is necessary because
the SMM handler operates from a distinct address space (SMRAM), and hence, the
debug trap does not represent the normal system memory space.
If an SMM handler wishes to use the debug trap feature of the processor to debug SMM
handler code, it must first ensure that an SMM-compliant debug handler is available.
The SMM handler must also ensure DR3:0 is saved to be restored later. The debug
registers DR3:0 and DR7 must then be initialized with the appropriate values.
If the processor wishes to use the single step feature of the processor, it must ensure
that an SMM compliant single step handler is available and then set the trap flag in the
EFLAGS register.
If the system design requires the processor to respond to hardware INTR requests
while in SMM, it must ensure that an SMM compliant interrupt handler is available and
then set the interrupt flag in the EFLAGS register (using the STI instruction). Software
interrupts are not blocked upon entry to SMM, and the system software designer must
provide an SMM compliant interrupt handler before attempting to execute any software
interrupt instructions. Note that in SMM mode, the interrupt vector table has the same
properties and location as the Real Mode vector table.
NMI interrupts are blocked upon entry to the SMM handler. If an NMI request occurs
during the SMM handler, it is latched and serviced after the processor exits SMM. Only
one NMI request is latched during the SMM handler. If an NMI request is pending when
the processor executes the RSM instruction, the NMI is serviced before the next
instruction of the interrupted code sequence.
Although NMI requests are blocked when the processor enters SMM, they may be
enabled through software by executing an IRET instruction. If the SMM handler
requires the use of NMI interrupts, it should invoke a dummy interrupt service routine
for the purpose of executing an IRET instruction. Once an IRET instruction is executed,
NMI interrupt requests are serviced in the same “Real Mode” manner in which they are
handled outside of SMM.