Specifications

Intel
®
Quark Core—Contents
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
14 Order Number: 329679-001US
113 Snoop Cycle Invalidating a Modified Line ...................................................................231
114 Snoop Cycle Overlaying a Line-Fill Cycle....................................................................232
115 Snoop Cycle Overlaying a Non-Burst Cycle.................................................................233
116 Snoop to the Line that is Being Replaced ...................................................................234
117 Snoop under BOFF# during a Cache Line-Fill Cycle......................................................236
118 Snoop under BOFF# to the Line that is Being Replaced................................................237
119 Snoop under HOLD during Line Fill............................................................................238
120 Snoop using HOLD during a Non-Cacheable, Non-Burstable Code Prefetch .....................239
121 Locked Cycles (Back-to-Back) ..................................................................................240
122 Snoop Cycle Overlaying a Locked Cycle .....................................................................241
123 Flush Cycle............................................................................................................242
124 Snoop under AHOLD Overlaying Pseudo-Locked Cycle .................................................243
125 Snoop under HOLD Overlaying Pseudo-Locked Cycle ...................................................244
126 Snoop under BOFF# Overlaying a Pseudo-Locked Cycle...............................................245
127 Size Breakpoint Fields.............................................................................................248
128 General Instruction Format .....................................................................................253
129 Intel
®
Quark SoC X1000 Core Cache Test Registers....................................................296
130 TR4 Definition for Standard and Enhanced Bus Modes for the Write-Back Enhanced
Intel
®
Quark SoC X1000 Core..................................................................................300
131 TR5 Definition for Standard and Enhanced Bus Modes for the Write-Back Enhanced
Intel
®
Quark SoC X1000 Core..................................................................................300
132 TLB Organization....................................................................................................301
133 TLB Test Registers..................................................................................................302
134 TAP Controller State Diagram...................................................................................305
Tables
1 Manual Contents ......................................................................................................17
2 Related Documents...................................................................................................20
3 Segment Register Selection Rules...............................................................................25
4 BASE and INDEX Registers for 16- and 32-Bit Addresses ...............................................28
5 Interrupt Vector Assignments.....................................................................................35
6 FPU Interrupt Vector Assignments ..............................................................................35
7 Sequence of Exception Checking.................................................................................37
8 Interrupt Vectors Used by FPU ...................................................................................38
9 Data Type Alignment Requirements ............................................................................42
10 Intel
®
Quark SoC X1000 Core Operating Modes............................................................48
11 On-Chip Cache Control Modes ....................................................................................48
12 Recommended Values of the Floating-Point Related Bits for Intel
®
Quark SoC X1000
Core.......................................................................................................................50
13 Interpreting Different Combinations of EM, TS and MP Bits.............................................50
14 Condition Code Interpretation after FPREM and FPREM1 Instructions ...............................56
15 Floating-Point Condition Code Interpretation ................................................................56
16 Condition Code Resulting from Comparison..................................................................57
17 Condition Code Defining Operand Class .......................................................................57
18 FPU Exceptions ........................................................................................................58
19 Debug Registers.......................................................................................................62
20 Test Registers..........................................................................................................62
21 Register Usage.........................................................................................................63
22 FPU Register Usage Differences..................................................................................63
23 MSRs for Intel
®
Quark Core 1 ....................................................................................64
24 Instruction Forms in which LOCK Prefix Is Legal............................................................65
25 Exceptions with Different Meanings in Real Mode (see Table 24) .....................................67
26 Access Rights Byte Definition for Code and Data Descriptions .........................................74
27 Pointer Test Instructions............................................................................................85