Specifications

Intel
®
Quark Core—System Management Mode (SMM) Architectures
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
146 Order Number: 329679-001US
8.6.2.2 Snoop During SMM
Snoops cycles are allowed during SMM. However, because the SMRAM is always cached
as a write-through, there can never be a snoop hit to a modified line in the SMRAM
address space. Consequently, if there is a snoop hit to a modified line, it corresponds to
the normal address space. In this case, even though SMIACT# is asserted, the memory
controller must drive the snoop write-back cycle to the normal memory space and not
to the SMRAM address space.
If the overlaid normal memory is cacheable, FLUSH# must be asserted when entering
SMM, causing all modified lines of normal memory to be written back. As a result, there
cannot be a snoop hit to a modified line in the cacheable normal memory space that is
overlaid with the SMRAM space.
If the overlaid normal memory is not cacheable, no flushing is necessary when entering
SMM. If normal memory is not overlaid with SMRAM, no flushing is required upon
entering SMM and it is possible that a snoop can hit a modified line cached from
anywhere in normal memory space while the processor is in SMM.
8.6.3 A20M# Pin and SMBASE Relocation
Note: The implementation of Intel
®
Quark Core on Intel
®
Quark SoC X1000 does not use the
A20M# pin; it is tied to 1'b1.
Systems based on a PC-compatible architecture contain a feature that enables the
processor address bit A20 to be forced to 0. This limits physical memory to a maximum
of 1 Mbyte, and is provided to ensure compatibility with those programs that relied on
the physical address wrap around functionality of the 8088 processor. The A20M# pin
on Intel
®
Quark SoC X1000 Core provides this function. When A20M# is active, all
external bus cycles drive A20M# low, and all internal cache accesses are performed
with A20M# low.
The A20M# pin is recognized while the processor is in SMM. The functionality of the
A20M# input must be recognized in the following two instances:
1. If the SMM handler needs to access system memory space above 1 Mbyte (for
example, when saving memory to disk for a zero-volt suspend), the A20M# pin
must be deasserted before the memory above 1 Mbyte is addressed.
2. If SMRAM has been relocated to address space above 1 Mbyte, and A20M# is active
upon entering SMM, the processor attempts to access SMRAM at the relocated
address, but with A20 low. This could cause the system to crash, because there
would be no valid SMM interrupt handler at the accessed location.
In order to account for the above two situations, the system designer must ensure that
A20M# is deasserted on entry to SMM. A20M# must be driven inactive before the first
cycle of the SMM state save, and must be returned to its original level after the last
cycle of the SMM state restore. This can be done by blocking the assertion of A20M#
when SMIACT# is active.
8.6.4 Processor Reset During SMM
The system designer should take into account the following restrictions while
implementing the processor RESET logic:
1. When running software written for the 80286 processor, an SRESET is used to
switch the processor from Protected Mode to Real Mode. Note that SRESET has a
higher interrupt priority than SMIACT#. When the processor is in SMM, the SRESET
to the processor during SMM should be blocked until the processor exits SMM.
SRESET must be blocked starting from the time SMI# is driven active and ending at