Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 149
Hardware Interface—Intel
®
Quark Core
9.0 Hardware Interface
9.1 Introduction
The Intel
®
Quark SoC X1000 Core has separate parallel buses for addresses and data.
The bidirectional data bus is 32 bits wide. The address bus consists of two components:
30 address lines (A[31:2]) and 4-byte enable lines (BE[3:0]#). The address lines form
the upper 30 bits of the address and the byte enables select individual bytes within a
4-byte location. The address lines are bidirectional for use in cache line invalidations
(see Figure 69).
The Intel
®
Quark SoC X1000 Core’s burst bus mechanism enables high-speed cache
fills from external memory. Burst cycles can strobe data into the processor at a rate of
one item every clock. Non-burst cycles have a maximum rate of one item every two
clocks. Burst cycles are not limited to cache fills: all read bus cycles requiring more
than a single data cycle can be burst.
During bus hold, the Intel
®
Quark SoC X1000 Core relinquishes control of the local bus
by floating its address, data, and control lines. The Intel
®
Quark SoC X1000 Core has
an address hold (AHOLD) feature in addition to bus hold. During address hold, only the
address bus is floated; the data and control buses can remain active. Address hold is
used for cache line invalidations.
This section provides a brief description of the Intel
®
Quark SoC X1000 Core input and
output signals arranged by functional groups. The # symbol at the end of a signal name
indicates that the active or asserted state occurs when the signal is at a low voltage.
When # is not present after the signal name, the signal is active at a high voltage level.
The term “ready” is used to indicate that the cycle is terminated with RDY# or BRDY#.
This chapter and Chapter 10.0, “Bus Operation,” describe bus cycles and data cycles. A
bus cycle is at least two-clocks long and begins with ADS# active in the first clock, and
RDY# and/or BRDY# are active in the last clock. Data is transferred to or from the
Intel
®
Quark SoC X1000 Core during a data cycle. A bus cycle contains one or more
data cycles.