Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 153
Hardware Interface—Intel
®
Quark Core
9.2.5.3 Pseudo-Lock Output (PLOCK#)
The pseudo-lock feature allows atomic reads and writes of memory operands greater
than 32 bits. These operands require more than one cycle to transfer. The Intel
®
Quark
SoC X1000 Core asserts PLOCK# during segment table descriptor reads (64 bits) and
cache line fills (128 bits).
When PLOCK# is asserted, no other master is given control of the bus between cycles.
A bus hold request (HOLD) is not acknowledged during pseudo-locked reads and
writes, with one exception. During non-cacheable non-burst code prefetches, HOLD is
recognized on memory cycle boundaries even though PLOCK# is asserted. The Intel
®
Quark SoC X1000 Core drives PLOCK# active until the addresses for the last bus cycle
of the transaction have been driven, regardless of whether BRDY# or RDY# are
returned.
A pseudo-locked transfer is meaningful only if the memory operand is aligned and if it
is completely contained within a single cache line.
Because PLOCK# is a function of the bus size and KEN# inputs, PLOCK# should be
sampled only in the clock ready is returned. PLOCK# is active low and is not driven
during bus hold (see Section 10.3.7).
9.2.5.4 PLOCK# Floating-Point Considerations
For processors with an on-chip FPU, the following must be noted for PLOCK# operation.
A 64-bit floating-point number must be aligned to an 8-byte boundary to guarantee an
atomic access. Normally, PLOCK# and BLAST# are inverses of each other. However,
during the first cycle of a 64-bit floating-point write, both PLOCK# and BLAST# are
asserted. Intel
®
Quark SoC X1000 Core with on-chip FPUs also assert PLOCK# during
floating-point long reads and writes (64 bits), segmentable description reads (64 bits),
and code line fills (128 bits).
9.2.6 Bus Control
The bus control signals allow the Intel
®
Quark SoC X1000 Core to indicate when a bus
cycle has begun, and allow other system hardware to control burst cycles, data bus
width, and bus cycle termination.
9.2.6.1 Address Status Output (ADS#)
The ADS# output indicates that the address and bus cycle definition signals are valid.
This signal goes active in the first clock of a bus cycle and goes inactive in the second
and subsequent clocks of the cycle. ADS# is also inactive when the bus is idle.
ADS# is used by the external bus circuitry as the indication that the Intel
®
Quark SoC
X1000 Core has started a bus cycle. The external circuit must sample the bus cycle
definition pins on the next rising edge of the clock after ADS# is driven active.
ADS# is active low and is not driven during bus hold.
9.2.6.2 Non-Burst Ready Input (RDY#)
RDY# indicates that the current bus cycle is complete. In response to a read, RDY#
indicates that the external system has presented valid data on the data pins. In
response to a write request, RDY# indicates that the external system has accepted the
Intel
®
Quark SoC X1000 Core data. RDY# is ignored when the bus is idle and at the
end of the first clock of the bus cycle. Because RDY# is sampled during address hold,
data can be returned to the processor when AHOLD is active.