Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 155
Hardware Interface—Intel
®
Quark Core
9.2.8.2 Soft Reset Input (SRESET)
The SRESET (soft reset) input has the same functions as RESET, but does not change
the SMBASE, and RESERVED# is not sampled on the falling edge of SRESET. If the
system uses SMBASE relocation, the soft resets should be handled using the SRESET
input. SRESET should not be used for the cold boot-up power-on reset.
The SRESET input pin is provided to save the status of SMBASE during a mode change.
SRESET leaves the location of SMBASE intact while resetting other units, including the
on-chip cache. See Section 9.2.17.4 for Write-Back Enhanced Intel
®
Quark SoC X1000
Core differences for SRESET. For compatibility, the system should use SRESET to flush
the on-chip cache. The FLUSH# input pin should be used to flush the on-chip cache.
SRESET should not be used to initiate test modes.
9.2.8.3 System Management Interrupt Request Input (SMI#)
SMI# is the system management mode interrupt request signal. The SMI# request is
acknowledged by the SMIACT# signal. After the SMI# interrupt is recognized, the
SMI# signal is masked internally until the RSM instruction is executed and the interrupt
service routine is complete. SMI# is falling-edge sensitive after internal
synchronization.
The SMI# input must be held inactive for at least four clocks after it is asserted to reset
the edge triggered logic. SMI# is provided with a pull-up resistor to maintain
compatibility with designs that do not use this feature. SMI# is an asynchronous signal,
but setup and hold times t
20
and t
21
must be met in order to guarantee recognition on a
specific clock.
9.2.8.4 System Management Mode Active Output (SMIACT#)
SMIACT# indicates that the processor is operating in System Management Mode. The
processor asserts SMIACT# in response to an SMI interrupt request on the SMI# pin.
SMIACT# is driven active after the processor has completed all pending write cycles
(including emptying the write buffers), and before the first access to SMRAM, in which
the processor saves (writes) its state (or context) to SMRAM. SMIACT# remains active
until the last access to SMRAM when the processor restores (reads) its state from
SMRAM. The SMIACT# signal does not float in response to HOLD. The SMIACT# signal
is used by the system logic to decode SMRAM.
9.2.8.5 Maskable Interrupt Request Input (INTR)
INTR indicates that an external interrupt has been generated. Interrupt processing is
initiated when the IF flag is active in the EFLAGS register.
The Intel
®
Quark SoC X1000 Core generates two locked interrupt acknowledge bus
cycles in response to asserting the INTR pin. An 8-bit interrupt number is latched from
an external interrupt controller at the end of the second interrupt acknowledge cycle.
INTR must remain active until the interrupt acknowledges have been performed to
assure program interruption. Refer to Section 10.3.10 for a detailed discussion of
interrupt acknowledge cycles.
The INTR pin is active high and is not provided with an internal pull-down resistor. INTR
is asynchronous, but the INTR setup and hold times t
20
and t
21
must be met to assure
recognition on any specific clock.