Specifications

Intel
®
Quark Core—Hardware Interface
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
156 Order Number: 329679-001US
9.2.8.6 Non-maskable Interrupt Request Input (NMI)
NMI is the non-maskable interrupt request signal. Asserting NMI causes an interrupt
with an internally supplied vector value of 2. External interrupt acknowledge cycles are
not generated because the NMI interrupt vector is internally generated. When NMI
processing begins, the NMI signal is masked internally until the IRET instruction is
executed.
NMI is rising edge sensitive after internal synchronization. NMI must be held low for at
least four CLK periods before this rising edge for proper operation. NMI is not provided
with an internal pull-down resistor. NMI is asynchronous but setup and hold times, t
20
and t
21
must be met to assure recognition on any specific clock.
9.2.8.7 Stop Clock Interrupt Request Input (STPCLK#)
The Intel
®
Quark SoC X1000 Core provides an interrupt mechanism, STPCLK#, that
allows system hardware to control the processor’s power consumption. The STPCLK#
signal can be asserted to stop the internal clock (output of the PLL) to the processor
core in a controlled manner. This low-power state is called the Stop Grant state. In
addition, the STPCLK# interrupt allows the system to change the input frequency
within the specified range or completely stop the CLK input frequency (input to the
PLL). If the CLK input is completely stopped, the processor enters into the Stop Clock
state—the lowest power state. If the frequency is changed or stopped, the Intel
®
Quark SoC X1000 Core does not return to the Stop Grant state until the CLK input has
been running at a constant frequency for the time period necessary to stabilize the PLL
(minimum of 1 ms).
The Intel
®
Quark SoC X1000 Core generates a Stop Grant bus cycle in response to the
STPCLK# interrupt request. STPCLK# is active low and is provided with an internal pull-
up resistor. STPCLK# is an asynchronous signal, but must remain active until the
processor issues the Stop Grant bus cycle (see Section 10.3.11.3).
9.2.9 Bus Arbitration Signals
This section describes the mechanism by which the processor relinquishes control of its
local bus when the local bus is requested by another bus master.
9.2.9.1 Bus Request Output (BREQ)
The Intel
®
Quark SoC X1000 Core asserts BREQ when a bus cycle is pending internally.
Thus, BREQ is always asserted in the first clock of a bus cycle, along with ADS#. If the
Intel
®
Quark SoC X1000 Core currently is not driving the bus (due to HOLD, AHOLD, or
BOFF#), BREQ is asserted in the same clock that ADS# would have been asserted if the
Intel
®
Quark SoC X1000 Core were driving the bus. After the first clock of the bus
cycle, BREQ may change state. It is asserted if additional cycles are necessary to
complete a transfer (via BS8#, BS16#, KEN#), or if more cycles are pending internally.
However, if no additional cycles are necessary to complete the current transfer, BREQ
can be negated before ready comes back for the current cycle. External logic can use
the BREQ signal to arbitrate among multiple processors. This pin is driven regardless of
the state of bus hold or address hold. BREQ is active high and is never floated. During a
hold state, internal events may cause BREQ to be de-asserted prior to any bus cycles.
9.2.9.2 Bus Hold Request Input (HOLD)
HOLD allows another bus master complete control of the Intel
®
Quark SoC X1000 Core
bus. The Intel
®
Quark SoC X1000 Core responds to an active HOLD signal by asserting
HLDA and placing most of its output and input/output pins in a high impedance state
(floated) after completing its current bus cycle, burst cycle, or sequence of locked
cycles. In addition, if the Intel
®
Quark SoC X1000 Core receives a HOLD request while