Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 165
Hardware Interface—Intel
®
Quark Core
In addition to using TCK as a free running clock, it may be stopped in a low, O, state,
indefinitely as described in IEEE 1149.1. While TCK is stopped in the low state, the
JTAG latches retain their state.
TCK is a clock signal and is used as a reference for sampling other JTAG signals. On the
rising edge of TCK, TMS and TDI are sampled. On the falling edge of TCK, TDO is
driven.
9.2.18.2 Test Mode Select (TMS)
TMS is decoded by the JTAG TAP (Test Access Port) to select the operation of the test
logic, as described in Section B.3.1.
To guarantee deterministic behavior of the TAP controller, TMS is provided with an
internal pull-up resistor. If JTAG is not used, TMS may be tied high or left unconnected.
TMS is sampled on the rising edge of TCK. TMS is used to select the internal TAP states
required to load JTAG instructions to data on TDI. For proper initialization of the JTAG
logic, TMS should be driven high, “1,” for at least four TCK cycles following the rising
edge of RESET.
9.2.18.3 Test Data Input (TDI)
TDI is the serial input used to shift JTAG instructions and data into the component. The
shifting of instructions and data occurs during the SHIFT-IR and SHIFT-DR TAP
controller states, respectively. These states are selected using the TMS signal, as
described in Section B.3.1, “Test Access Port (TAP) Controller” on page 304.
An internal pull-up resistor is provided on TDI to ensure a known logic state if an open
circuit occurs on the TDI path. Note that when “1” is continuously shifted into the
instruction register, the BYPASS instruction is selected. TDI is sampled on the rising
edge of TCK, during the SHIFT-IR and the SHIFT-DR states. During all other TAP
controller states, TDI is a “don't care.” TDI is sampled only when TMS and TCK have
been used to select the SHIFT-IR or SHIFT-DR states in the TAP controller. For proper
initialization of JTAG logic, TDI should be driven high for at least four TCK cycles
following the rising edge of RESET.
9.2.18.4 Test Data Output (TDO)
TDO is the serial output used to shift JTAG instructions and data out of the component.
The shifting of instructions and data occurs during the SHIFT-IR and SHIFT-DR TAP
controller states, respectively. These states are selected using the TMS signal, as
described in Section B.3.1, “Test Access Port (TAP) Controller” on page 304. When not
in SHIFT-IR or SHIFT-DR states, TDO is driven to a high impedance state to allow
connecting TDO to different devices in parallel. TDO is driven on the falling edge of TCK
during the SHIFT-IR and SHIFT-DR TAP controller states. At all other times TDO is
driven to the high impedance state. TDO is only driven when TMS and TCK have been
used to select the SHIFT-IR or SHIFT-DR states in the TAP controller.
9.3 Interrupt and Non-Maskable Interrupt Interface
The Intel
®
Quark SoC X1000 Core provides four asynchronous interrupt inputs: INTR
(interrupt request), NMI (non-maskable interrupt), SMI# (system management
interrupt) and STPCLK# (stop clock interrupt). This section describes the hardware
interface between the instruction execution unit and the pins. For a description of the
algorithmic response to interrupts, refer to Section 3.7. For interrupt timings refer to
Section 10.3.10.