Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 17
About this Manual—Intel
®
Quark Core
1.0 About this Manual
This manual describes the embedded Intel
®
Quark SoC X1000 Core. It is intended for
use by hardware designers familiar with the principles of embedded microprocessors
and with the Intel
®
Quark SoC X1000 Core architecture.
1.1 Manual Contents
Table 1 summarizes the contents of the remaining chapters and appendixes. The
remainder of this chapter describes notation conventions and special terminology used
throughout the manual and provides references to related documentation.
Table 1. Manual Contents (Sheet 1 of 2)
Chapter Description
Chapter 2.0, “Intel
®
Quark SoC X1000 Core
Overview”
Provides an overview of the current embedded Intel
®
Quark SoC X1000 Core,
including product features, system components, system architecture, and
applications. This chapter also lists product frequency, voltage, and package
offerings.
Chapter 3.0,
“Architectural Overview”
Describes the Intel
®
Quark SoC X1000 Core internal architecture, with an
overview of the processor’s functional units.
Chapter 4.0, “System
Register Organization”
Details the Intel
®
Quark SoC X1000 Core register set, including the base
architecture registers, system-level registers, debug and test registers, and Intel
®
Quark SoC X1000 Core Model Specific Registers (MSRs).
Chapter 5.0, “Real Mode
Architecture”
When the Intel
®
Quark SoC X1000 Core is powered-up, it is initialized in Real
Mode, which is described in this chapter.
Chapter 6.0, “Protected
Mode Architecture”
Describes Protected Mode, including segmentation, protection, and paging.
Chapter 7.0, “On-Chip
Cache”
The Intel
®
Quark SoC X1000 Core contains an on-chip cache, also known as L1
cache. This chapter describes its functionality.
Chapter 8.0, “System
Management Mode
(SMM) Architectures”
Describes the System Management Mode architecture of the Intel
®
Quark SoC
X1000 Core, including System Management Mode interrupt processing and
programming.
Chapter 9.0, “Hardware
Interface”
Describes the hardware interface of the Intel
®
Quark SoC X1000 Core, including
signal descriptions, interrupt interfaces, write buffers, reset and initialization, and
clock control.
Chapter 10.0, “Bus
Operation”
Describes the features of the processor bus, including bus cycle handling,
interrupt and reset signals, cache control, and floating-point error control.
Chapter 11.0,
“Debugging Support”
Describes the Intel
®
Quark SoC X1000 Core debugging support, including the
breakpoint instruction, single-step trap, and debug registers.
Chapter 12.0,
“Instruction Set
Summary”
Describes the Intel
®
Quark SoC X1000 Core instruction set and the encoding of
each field within the instructions.