Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 171
Hardware Interface—Intel
®
Quark Core
9.5.2 Pin State During Reset
The Intel
®
Quark SoC X1000 Core recognizes and can respond to HOLD, AHOLD, and
BOFF# requests regardless of the state of RESET. Thus, even though the processor is in
reset, it can float its bus in response to any of these requests.
While in reset, the Intel
®
Quark SoC X1000 Core bus is in the state shown in Figure 72
if the HOLD, AHOLD and BOFF# requests are inactive. Note that the address (A[31:2],
BE[3:0]#) and cycle definition (M/IO#, D/C#, W/R#) pins are undefined from the time
reset is asserted until the start of the first bus cycle. All undefined pins (except FERR#)
assume known values at the beginning of the first bus cycle. The first bus cycle is
always a code fetch to address FFFFFFF0H.
FEA 00000000h Unchanged
FCS 0000h Unchanged
FDS 0000h Unchanged
FOP 000h Unchanged
FSTACK Undefined Unchanged
Table 56. Floating-Point Values after Reset (Sheet 2 of 2)