Specifications

Intel
®
Quark Core—Hardware Interface
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
172 Order Number: 329679-001US
Figure 72. Pin States During RESET
CLK
RESET
AHOLD
FLUSH#
Sync)
FLUSH#
(Async)
A20M#
(Sync)
A20M#
(Async)
ADS#
BREQ
A31:4,
MIO#,
BLAST
A3, A2,
PLOCK
D/C#, W/R#,
PCHK#
LOCK#
D[31:0]
HLDA
SMIACT#
WB/WT#
CACHE#
HITM#
T
X
T
X
T
X
T
X
T
I
T
I
T
I
T
I
At least 15 CLK periods
(8)
~2
17
CLK if no self-test
~2
20
CLK if no self-test
(1)
T20
(1)
T20
(6)
(4)
(5)
(2)
(3)
U
NDEFINED
UNDEFINED
(7)
(9)
(10)
INPUTS
OUTPUTS
See notes on next page.