Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 173
Hardware Interface—Intel
®
Quark Core
9.5.2.1 Controlling the CLK Signal in the Processor during Power On
Intel does not specify the power on requirements of the Intel
®
Quark SoC X1000 Core
allowable CLK input during the power on sequence. Clocking the processor before V
CC
reaches its normal operating level can cause unpredictable results on Intel
®
Quark SoC
X1000 Core. The information in this section reflects what Intel considers a good clock
design.
Intel strongly recommends that system designers ensure that a clock signal is not
presented to the Intel
®
Quark SoC X1000 Core until V
CC
has stabilized at its normal
operating level. This design recommendation can easily be met by gating the clock
signal with a POWERGOOD signal. The POWERGOOD signal should reflect the status of
V
CC
at the Intel
®
Quark SoC X1000 Core (which may be different from the power
supply status in designs that provide power to the processor using a voltage regulator
or converter).
Most clock synthesizers and some clock oscillators contain on-board gating logic. If
external gating logic is implemented, it should be done on the original clock signal
output from the clock oscillator/synthesizer. Gating the clock to the processor
independently of the clock to the rest of the motherboard causes clock skew, which
may violate processor or chipset timing requirements. If the clock signal to the
motherboard is enabled with a POWERGOOD signal, verify that the motherboard logic
does not require a clock input prior to this POWERGOOD signal. Some chipsets also
gate the clock to the processor only after a POWERGOOD signal, which inherently
meets the requirements of this design. Designs should implement the design as
described in this section to maintain maximum flexibility with all Intel
®
Quark SoC
X1000 Core steppings.
9.5.2.2 FERR# Pin State During Reset for Intel
®
Quark SoC X1000 Core
FERR# reflects the state of the ES (error summary status) bit in the floating-point unit
status word. The ES bit is initialized when the floating-point unit state is initialized. The
floating-point unit's status word register can be initialized by BIST or by executing the
FINIT/FNINIT instruction. Thus, after reset and before executing the first FINIT or
FNINIT instruction, the values of the FERR# and the numeric status word register bits
Notes to Figure 72:
1. RESET is an asynchronous input. t
20
must be met only to guarantee recognition on a specific clock
edge.
2. When A20M# is driven synchronously, it must be driven high (inactive) for the CLK edge prior to
the falling edge of RESET to ensure proper operation. A20M# setup and hold times must be met.
Intel
®
Quark Core on Intel
®
Quark SoC X1000 does not use the A20M# pin; it is tied to 1'b1.
3. When A20M# is driven asynchronously, it should be driven low (active) for two CLKs prior to and
two CLKs after the falling edge of RESET to ensure proper operation.
Intel
®
Quark Core on Intel
®
Quark SoC X1000 does not use the A20M# pin; it is tied to 1'b1.
4. When FLUSH# is driven synchronously, it must be driven low (high) for the CLK edge prior to the
falling edge of RESET to invoke the three-state Output Test Mode. All outputs are guaranteed
three-stated within 10 CLKs of RESET being de-asserted. FLUSH# setup and hold times must be
met.
5. When FLUSH# is driven asynchronously, it must be driven low (active) for two CLKs prior to and
two CLKs after the falling edge of RESET to invoke the three-state Output Test Mode. All outputs
are guaranteed three-stated within 10 CLKs of RESET being de-asserted.
6. AHOLD should be driven high (active) for the CLK edge prior to the falling edge of RESET to invoke
the Built-in Self Test (BIST). AHOLD setup and hold times must be met.
7. Hold is recognized normally during RESET. On power-up, HLDA is indeterminate until RESET is
recognized by the processor.
8. 15 CLKs RESET pulse width for warm resets. Power-up resets require RESET to be asserted for at
least 1 ms after V
CC
and CLK are stable.
9. WB/WT# should be driven high for at least one CLK before the falling edge of RESET and at least
one CLK after the falling edge of RESET to enable the Enhanced Bus mode. Standard Bus mode is
enabled if WB/WT# is sampled low or left floating at the falling edge of RESET.
10. The system may sample HITM# to detect the presence of the Enhanced Bus mode. If HITM# is
high for one CLK after RESET is inactive, Enhanced Bus mode is present.