Specifications

Intel
®
Quark Core—Hardware Interface
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
174 Order Number: 329679-001US
7:0 depend on whether or not BIST is performed. Table 57 shows the state of FERR#
signal after reset and before the execution of the FINIT/FNINIT instruction.
After the first FINIT or FNINIT instruction, FERR# and the FPU status word register bits
(7:0) are inactive, irrespective of the Built-In Self-Test (BIST).
9.5.2.3 Power Down Mode (In-circuit Emulator Support)
The Power Down mode on the Intel
®
Quark SoC X1000 Core, when initiated by the
Reserved# signal, reduces the power consumption of the Intel
®
Quark SoC X1000
Core, as well as forces all of its output signals to be three-stated. The RERSERVED# pin
on the Intel
®
Quark SoC X1000 Core is used for enabling the Power Down mode.
When the RESERVED# pin is driven active upon power-up, the Intel
®
Quark SoC X1000
Core's bus is floated immediately. The Intel
®
Quark SoC X1000 Core enters Power
Down mode when the RESERVED# pin is sampled asserted in the clock before the
falling edge of RESET. The RESERVED# pin has no effect on the power down status,
except during this edge. The Intel
®
Quark SoC X1000 Core then remains in the Power
Down mode until the next time the RESET signal is activated. For warm resets, with the
upgrade processor in the system, the Intel
®
Quark SoC X1000 Core remains three-
stated and re-enters the Power Down mode once RESET is de-asserted. Similarly for
power-up resets, if the upgrade processor is not taken out of the system, the Intel
®
Quark SoC X1000 Core three-states its outputs upon sensing the RESERVED# pin
active and enters the Power Down Mode after the falling edge of RESET.
9.6 Clock Control
The Intel
®
Quark SoC X1000 Core provides an interrupt mechanism (STPCLK#) that
allows system hardware to control the power consumption of the processor by stopping
the internal clock (output of the PLL) to the processor core in a controlled manner. This
low-power state is called the Stop Grant state. In addition, the STPCLK# interrupt
allows the system to change the input frequency within the specified range or
completely stop the CLK input frequency (an input to the PLL). If the CLK input is
stopped completely, the processor enters into the Stop Clock state—the lowest power
state.
See Section 9.6.4.2 and Section 9.6.4.3, for a detailed description of the Stop Grant
and Stop Clock states, respectively.
9.6.1 Stop Grant Bus Cycles
A special Stop Grant bus cycle is driven to the bus after the processor recognizes the
STPCLK# interrupt. The definition of this bus cycle is the same as the HALT cycle
definition for the standard Intel
®
Quark SoC X1000 Core, with the exception that the
Stop Grant bus cycle drives the value 0000 0010H on the address pins. The system
hardware must acknowledge this cycle by returning RDY# or BRDY#. The processor
does not enter the Stop Grant state until either RDY# or BRDY# has been returned.
The Stop Grant bus cycle is defined as follows:
Table 57. FERR# Pin State after Reset and before FP Instructions
BIST Performed FERR# Pin FPU Status Word Register Bits 7:0
YES Inactive (High) Inactive (Low)
NO Undefined (Low or High) Undefined (Low or High)