Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 177
Hardware Interface—Intel
®
Quark Core
The Write-Back Enhanced Intel
®
Quark SoC X1000 Core has bus keepers features. The
data bus and data parity pins have bus keepers that maintain the previous state while
in the Stop Grant state. External resistors are no longer required, which prevents
excess current during the Stop Grant state. (If external resistors are present, they
should be strong enough to “flip” the bus hold circuitry and eliminate potential DC
paths. Alternately, “weak” resistors may be added to prevent excessive current flow.)
In order to obtain the lowest possible power consumption during the Stop Grant state,
system designers must ensure that the input signals with pull-up resistors are not
driven low, and the input signals with pull-down resistors are not driven high.
9.6.4 Clock Control State Diagram
The following state descriptions and diagram show the state transitions during a Stop
Clock cycle for the Intel
®
Quark SoC X1000 Core. (Refer to Figure 74 for a Stop Clock
state diagram.) Refer to Section 9.6.5 for Write-Back Enhanced Intel
®
Quark SoC
X1000 Core Clock Control State specifics.
9.6.4.1 Normal State
This is the normal operating state of the processor.
9.6.4.2 Stop Grant State
The Stop Grant state provides a fast wake-up state that can be entered by simply
asserting the external STPCLK# interrupt pin. Once the Stop Grant bus cycle has been
placed on the bus, and either RDY# or BRDY# is returned, the processor is in this state
(depending on the CLK input frequency). The processor returns to the normal execution
state approximately 10–20 clock periods after STPCLK# has been de-asserted.
While in the Stop Grant state, the pull-up resistors on STPCLK#, CLKMUL (for the
Intel
®
Quark SoC X1000 Core) and RESERVED# are disabled internally. The system
must continue to drive these inputs to the state they were in immediately before the
processor entered the Stop Grant state. For minimum processor power consumption,
all other input pins should be driven to their inactive level while the processor is in the
Stop Grant state.
A RESET or SRESET brings the processor from the Stop Grant state to the Normal
state. The processor recognizes the inputs required for cache invalidations (HOLD,
AHOLD, BOFF# and EADS#), as explained later in this section. The processor does not
recognize any other inputs while in the Stop Grant state. Input signals to the processor
BLAST# O Previous state
FERR# O Previous state
PCHK# O Previous state
PWT, PCD O Previous state
CACHE# O Inactive
(1)
(high)
HITM# O Inactive
(1)
(high)
SMIACT# O Previous state
Table 59. Write-Back Enhanced Intel
®
Quark SoC X1000 Core Pin States
during Stop Grant Bus Cycle (Sheet 2 of 2)
Signal Type State
Notes:
1. For the case of snoop cycles (via EADS#) during Stop Grant state, both HITM#
and CACHE# may go active depending on the snoop hit in the internal cache.
2. During Stop Grant state, AHOLD, HOLD, BOFF# and EADS# are serviced normally.