Specifications

Intel
®
Quark Core—Hardware Interface
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
178 Order Number: 329679-001US
are not recognized until one CLK after STPCLK# is de-asserted (see Figure 75).
While in the Stop Grant state, the processor does not recognize transitions on the
interrupt signals (SMI#, NMI, and INTR). Driving an active edge on either SMI# or NMI
does not guarantee recognition and service of the interrupt request following exit from
the Stop Grant state. However, if one of the interrupt signals (SMI#, NMI, or INTR) is
driven active while the processor is in the Stop Grant state, and held active for at least
one CLK after STPCLK# is de-asserted, the corresponding interrupt is serviced. The
Intel
®
Quark SoC X1000 Core requires INTR to be held active until the processor issues
an interrupt acknowledge cycle in order to guarantee recognition (see Figure 75).
When the processor is in the Stop Grant state, the system can stop or change the CLK
input. When the CLK input to the processor is stopped or changed, the Intel
®
Quark
SoC X1000 Core requires the CLK input to be held at a constant frequency for a
minimum of 1 ms before de-asserting STPCLK#. This 1-ms time period is necessary so
that the PLL can stabilize, and it must be met before the processor returns to the Stop
Grant state.
Figure 74. Intel
®
Quark SoC X1000 Core Stop Clock State Machine
The Intel
®
Quark SoC X1000 Core generates a Stop Grant bus cycle only when entering
that state from the Normal or the Auto HALT Power Down state. When the Intel
®
Quark
SoC X1000 Core enters the Stop Grant state from the Stop Clock state or the Stop
Clock Snoop state, the processor does not generate a Stop Grant bus cycle.
4. Auto HALT Power Down State
CLK Running
I
CC
~ 100 mA
1. Normal State
Normal Execution
HALT asserted and
HALT Bus cycle
generated
INTR, NMI, SMI#,
RESET, SRESET
2. Stop Grant State
Clock Running
I
CC
– 20 mA – 50 mA
STPCLK# asserted and
Stop Grant Bus cycle
generated
STPCLK# de-asserted and
HALT Bus cycle generated
STPCLK# asserted and
Stop Grant Bus cycle generated
5. Stop Clock Snoop State
One Clock Powerup
Perform Cache Invalidation
EADS#
EADS#
3. Stop Clock State
Internal Powerdown
CLK Changed
†
I
CC
~ 100 mA
STOP CLK
S
TART CLK
+ PLL S
TARTUP LATENCY
†
The system can change the input frequency within the
specified range or completely stop the CLK input frequency
Reset