Specifications

Intel
®
Quark Core—Hardware Interface
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
180 Order Number: 329679-001US
A FLUSH# event during the Stop Grant state or the Auto HALT Power Down state is
latched and acted upon by asserting the internal FLUSH# signal for one clock upon re-
entering the Normal state.
9.6.4.6 Auto Idle Power Down State
When the processor is known to be truly idle and waiting for RDY# or BRDY# from a
memory or I/O bus cycle read, the Intel
®
Quark SoC X1000 Core reduces its core clock
rate to equal that of the external CLK frequency without affecting performance. When
RDY# or BRDY# is asserted, the processor returns to clocking the core at the specified
multiplier of the external CLK frequency. This functionality is transparent to software
and external hardware.
9.6.5 Write-Back Enhanced Intel
®
Quark SoC X1000 Core Clock
Control State Diagram
Figure 76 shows the state transitions during Stop Clock for the Write-Back Enhanced
Intel
®
Quark SoC X1000 Core.
9.6.5.1 Normal State
This is the normal operating state of the processor. When the processor is executing
program/instruction and the STPCLK# pin is not asserted, the processor is said to be in
its Normal state.