Specifications
Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 181
Hardware Interface—Intel
®
Quark Core
Figure 76. Write-Back Enhanced Intel
®
Quark SoC X1000 Core Stop Clock State Machine
(Enhanced
Bus Configuration)
9.6.5.2 Stop Grant State
For minimum processor power consumption, all other input pins should be driven to
their inactive level while the processor is in the Stop Grant state except for the data
bus, data parity, WB/WT# and INV pins. WB/WT# should be driven low and INV should
be driven high.
In both the Standard mode and Enhanced mode, the following conditions exist:
• A RESET, SRESET or de-assertion of STPCLK# brings the processor from the Stop
Grant state to the Normal state.
• While in the Stop Grant state, the processor does not recognize transitions on the
interrupt signals (SMI#, NMI, and INTR). This means SMI#, NMI, and INTR are not
Stop Break events. The external logic should de-assert STPCLK# before issuing
interrupts, or if an interrupt is asserted it should be kept asserted for at least one
clock after STPCLK# is removed. (Note that the Write-Back Enhanced Intel
®
Quark
SoC X1000 Core requires that INTR be held active until the processor issues an
interrupt acknowledge cycle in order to guarantee recognition).
• FLUSH# is not a Stop Break event. But if FLUSH# is asserted during the Stop Grant
state, it is latched by the Write-Back Enhanced Intel
®
Quark SoC X1000 Core and
serviced later when STPCLK# is de-asserted.
4. Auto HALT Power Down State
CLK Running
I
CC
approximately 100
µA
1. Normal State
Normal Execution
HALT
INTR, NMI, SMI#,
RESET, SRESET
2. Stop Grant State
Clock Running
I
CC
Approximately 20 mA – 50 mA
STPCLK# asserted
STPCLK# de-asserted
STPCLK# asserted
5. Stop Clock Snoop State
Clock Powerup
EADS#
EADS#
3. Stop Clock State
Internal Powerdown
CLK Stopped
I
CC
Approximately 100 µA
STOP CLK
S
TART CLK
+ PLL S
TARTUP LATENCY
All Clocks Running
Reset
STPCLK#
asserted and
Stop Grant
bus cycles
Halt Bus Cycle Generated
6. Auto HALT Power Down
Flush State
Write through: Cache Invalidation
Write back: Write-back, Invalidation,
2 flush acknowledge cycles
FLUSH#
Write through: Cache Invalidation
Write back: Write, Invalidation
generated