Specifications

Intel
®
Quark Core—Hardware Interface
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
182 Order Number: 329679-001US
• The processor latches and responds to the inputs BOFF#, EADS#, AHOLD, and
HOLD. The processor does not recognize any other inputs while in the Stop Grant
state except FLUSH#. Other input signals to the processor are not recognized until
the CLK following the CLK in which STPCLK# is de-asserted (see Figure 76).
• The processor generates a Stop Grant bus cycle only when entering that state from
the Normal or the Auto HALT Power Down state. The Stop Grant bus cycle is not
generated when the processor enters the Stop Grant state from the Stop Clock
state or the Stop Clock Snoop state.
• The processor does not enter the Stop Grant state until all the pending writes are
completed, all pending interrupts are serviced, and the processor is idle.
9.6.5.3 Stop Clock State
The Stop Clock state is the lowest power consumption mode of the Intel
®
Quark SoC
X1000 Core, because it allows removal of the external clock. It also has the longest
latency for returning to normal state. The Stop Clock state is entered from the Stop
Grant state by stopping the CLK input. In the Stop Clock state, total processor power
consumption drops to 100 A, which is approximately 200–250 times lower than the
Stop Grant state. None of the processor input signals should change state while the
CLK input is stopped. Any transition on an input signal before the processor has
returned to the Stop Grant state results in unpredictable behavior. If INTR is driven
active, it must remain active until the processor issues an interrupt acknowledge cycle.
In the Stop Clock state, the processor is dormant. It does not respond to transitions on
any of the input pins, including snoops, flushes and interrupts. It is recommended that
this mode only be entered if the processor cache is coherent with main memory and
the processor is not processing interrupts. If this mode is entered with a dirty cache, no
alternate master cycles can be allowed while the processor is in the Stop Clock state.
The processor returns to the Stop Grant state after the CLK input has been running at a
constant frequency for a period of time equal to the PLL startup latency. The CLK input
can be restarted to any frequency between the minimum and maximum frequency
listed in the AC timing specifications.
In Enhanced Bus mode, if the processor is taken into the Stop Clock state with a dirty
cache, alternate bus master cycles are not allowed while the processor remains in the
Stop Clock state. In order to take the processor into the Stop Clock state with a clean
cache, the cache must be flushed. During the time the cache is being flushed, the
system must block interrupts to the processor. With all interrupts other than STPCLK#
blocked, the processor does not write into the cache during the time from the
completion of the flush and time it enters the Stop Grant state. This is necessary for
the cache to be coherent. To ensure cache coherency, the system should drive KEN#
inactive from the time the flush starts until the Stop Grant cycle is issued. The system
can then put the processor in the Stop Clock state by stopping the clock.
If the processor is already in the Stop Grant state and entering the Stop Clock state is
desired, the system must de-assert STPCLK# before flushing the cache in order to
ensure cache coherency. The five-clock de-assertion specification for STPCLK# must
also be met before the above sequence can occur.
9.6.5.4 Auto HALT Power Down State
Upon execution of a HALT instruction, the processor automatically enters a low power
state called the Auto HALT Power Down state. The processor issues a normal HALT bus
cycle when entering this state. Because interrupts are HALT break events, the
processor transitions to the Normal state on the occurrence of INTR, NMI, SMI# or
RESET (SRESET is also a HALT break event). If a FLUSH# occurs while the processor is