Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 187
Bus Operation—Intel
®
Quark Core
The external system must contain buffers to enable the Intel
®
Quark SoC X1000 Core
to read and write data on the appropriate data bus pins. Table 63 shows the data bus
lines to which the Intel
®
Quark SoC X1000 Core expects data to be returned for each
valid combination of byte enables and bus sizing options.
Valid data is only driven onto data bus pins corresponding to asserted byte enables
during write cycles. Other pins in the data bus are driven but they contain no valid
data. The Intel
®
Quark SoC X1000 Core does not duplicate write data onto parts of the
data bus for which the corresponding byte enable is deasserted.
10.1.3 Interfacing with 8-, 16-, and 32-Bit Memories
Note: The implementation of Intel
®
Quark Core on Intel
®
Quark SoC X1000 supports 32-bit
data mode only.
Table 62. Next Byte Enable Values for BSx# Cycles
Current Next with Next with BS16#
BE3# BE2# BE1# BE0# BE3# BE2# BE1# BE0# BE3# BE2# BE1# BE0#
1110NNNNNNNN
11001101NNNN
100010011011
000000010011
1101NNNNNNNN
100110111011
000100110011
1011NNNNNNNN
00110111NNNN
0111NNNNNNNN
Note: “N” means that another bus cycle is not required to satisfy the request.
Table 63. Data Pins Read with Different Bus Sizes
BE3# BE2# BE1# BE0# w/o BS8#/BS16# w BS8# w BS16#
1 1 1 0 D[7:0] D[7:0] D[7:0]
1 1 0 0 D[15:0] D[7:0] D[15:0]
1 0 0 0 D[23:0] D[7:0] D[15:0]
0 0 0 0 D[31:0] D[7:0] D[15:0]
1 1 0 1 D[15:8] D[15:8] D[15:8]
1 0 0 1 D[23:8] D[15:8] D[15:8]
0 0 0 1 D[31:8] D[15:8] D[15:8]
1 0 1 1 D[23:16] D[23:16] D[23:16]
0 0 1 1 D[31:16] D[23:16] D[31:16]
0 1 1 1 D[31:24] D[31:24] D[31:24]