Specifications

Intel
®
Quark Core—Bus Operation
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
190 Order Number: 329679-001US
Combinations of BE[3:0]# that never occur are those in which two or three asserted
byte enables are separated by one or more deasserted byte enables. These
combinations are “don't care” conditions in the decoder. A decoder can use the non-
occurring BE[3:0]# combinations to its best advantage.
Figure 82 shows a Intel
®
Quark SoC X1000 Core data bus interface to 16- and 8-bit
wide memories. External byte swapping logic is needed on the data lines so that data is
supplied to and received from the Intel
®
Quark SoC X1000 Core on the correct data
pins (see Table 63).
Figure 81. Logic to Generate A1, BHE# and BLE# for 16-Bit Buses