Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 191
Bus Operation—Intel
®
Quark Core
Figure 82. Data Bus Interface to 16- and 8-Bit Memories
10.1.4 Dynamic Bus Sizing during Cache Line Files
BS8# and BS16# can be driven during cache line fills. The Intel
®
Quark SoC X1000
Core generates enough 8- or 16-bit cycles to fill the cache line. This can be up to
sixteen 8-bit cycles.
The external system should assume that all byte enables are asserted for the first cycle
of a cache line fill. The Intel
®
Quark SoC X1000 Core generates proper byte enables for
subsequent cycles in the line fill. Table 65 shows the appropriate A0 (BLE#), A1 and
BHE# for the various combinations of the Intel
®
Quark SoC X1000 Core byte enables
on both the first and subsequent cycles of the cache line fill. The “†” marks all
combinations of byte enables that are generated by the Intel
®
Quark SoC X1000 Core
during a cache line fill.
Intel® Quark
Core
BS16#
BS8#
Address
Decode
32-Bit
Memory
16-Bit Memory
8-Bit Memory
Byte Swap
Logic
Byte Swap
Logic
16
8
8
8
8
8
D[7:0]
D[15:8]
D[23:16]
D[31:24]
(A[31:2], BE[3:0]#)
Table 65. Generating A0, A1 and BHE# from the Intel
®
Quark SoC X1000 Core Byte
Enables (Sheet 1 of 2)
BE3# BE2# BE1# BE0#
First Cache Fill Cycle Any Other Cycle
A0 A1 BHE# A0 A1 BHE#
1 110000001
1 100000000
1 000000000
†0 000000000
1 101000100
1 001000100
†0 001000100
1 011000011