Specifications

Intel
®
Quark Core—Bus Operation
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
192 Order Number: 329679-001US
10.1.5 Operand Alignment
Physical 4-byte words begin at addresses that are multiples of four. It is possible to
transfer a logical operand that spans more than one physical 4-byte word of memory or
I/O at the expense of extra cycles. Examples are 4-byte operands beginning at
addresses that are not evenly divisible by 4, or 2-byte words split between two physical
4-byte words. These are referred to as unaligned transfers.
Operand alignment and data bus size dictate when multiple bus cycles are required.
Table 66 describes the transfer cycles generated for all combinations of logical operand
lengths, alignment, and data bus sizing. When multiple cycles are required to transfer a
multibyte logical operand, the highest-order bytes are transferred first. For example,
when the processor executes a 4-byte unaligned read beginning at byte location 11 in
the 4-byte aligned space, the three high-order bytes are read in the first bus cycle. The
low byte is read in a subsequent bus cycle.
The function of unaligned transfers with dynamic bus sizing is not obvious. When the
external systems asserts BS16# or BS8#, forcing extra cycles, low-order bytes or
words are transferred first (opposite to the example above). When the Intel
®
Quark
SoC X1000 Core requests a 4-byte read and the external system asserts BS16#, the
lower two bytes are read first followed by the upper two bytes.
†0 011000010
†0 111000110
KEY:
† =a non-occurring pattern of Byte Enables; either none are asserted or the pattern has byte
enables asserted for non-contiguous bytes
Table 65. Generating A0, A1 and BHE# from the Intel
®
Quark SoC X1000 Core Byte
Enables (Sheet 2 of 2)
BE3# BE2# BE1# BE0#
First Cache Fill Cycle Any Other Cycle
A0 A1 BHE# A0 A1 BHE#
Table 66. Transfer Bus Cycles for Bytes, Words and Dwords
Byte-Length of Logical Operand
12 4
Physical Byte Address in
Memory (Low Order Bits)
xx 00 01 10 11 00 01 10 11
Transfer Cycles over 32-Bit
Bus
bwww
hb
lb
d
hb
l3
hw
lw
h3
lb
Transfer Cycles over 16-Bit
Bus
(† = BS#16 asserted)
bw
lb †
hb †
w
hb
lb
lw †
hw †
hb
lb †
mw †
hw
lw
mw †
hb †
lb
Transfer Cycles over 8-Bit
Bus
(‡ = BS8# Asserted)
b
lb ‡
hb ‡
lb ‡
hb‡
lb ‡
hb ‡
hb
lb
lb ‡
mlb ‡
mhb ‡
hb ‡
hb
lb ‡
mlb ‡
mhb ‡
mhb ‡
hb ‡
lb ‡
mlb ‡
mlb ‡
mhb ‡
hb ‡
lb
KEY:
b = byte transferh = high-order portion4-Byte Operand
w = 2-byte transferl = low-order portion
3 = 3-byte transferm = mid-order portion
d = 4-byte transfer
lb mlb mhb hb
↑ byte with
lowest address
↑byte with
highest
address