Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 193
Bus Operation—Intel
®
Quark Core
In the unaligned transfer described above, the processor requested three bytes on the
first cycle. When the external system asserts BS16# during this 3-byte transfer, the
lower word is transferred first followed by the upper byte. In the final cycle, the lower
byte of the 4-byte operand is transferred, as shown in the 32-bit example above.
10.2 Bus Arbitration Logic
Bus arbitration logic is needed with multiple bus masters. Hardware implementations
range from single-master designs to those with multiple masters and DMA devices.
Figure 83 shows a simple system in which only one master controls the bus and
accesses the memory and I/O devices. Here, no arbitration is required.
Figure 83. Single Master Intel
®
Quark Core System
Figure 84 shows a single processor and a DMA device. Here, arbitration is required to
determine whether the processor, which acts as a master most of the time, or a DMA
controller has control of the bus. When the DMA wants control of the bus, it asserts the
HOLD request to the processor. The processor then responds with a HLDA output when
it is ready to relinquish bus control to the DMA device. Once the DMA device completes
its bus activity cycles, it negates the HOLD signal to relinquish the bus and return
control to the processor.
Intel® Quark
Core
I/O
MEM
Control Bus
Data Bus
Address Bus