Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 195
Bus Operation—Intel
®
Quark Core
Figure 85. Single Intel
®
Quark Core with Multiple Secondary Masters
As systems become more complex and include multiple bus masters, hardware must be
added to arbitrate and assign the management of bus time to each master. The second
master may be a DMA controller that requires bus time to perform memory transfers or
it may be a second processor that requires the bus to perform memory or I/O cycles.
Any of these devices may act as a bus master. The arbitration logic must assign only
one bus master at a time so that there is no contention between devices when
accessing main memory.
The arbitration logic may be implemented in several different ways. The first technique
is to “round-robin” or to “time slice” each master. Each master is given a block of time
on the bus to match their priority and need for the bus.
Another method of arbitration is to assign the bus to a master when the bus is needed.
Assigning the bus requires the arbitration logic to sample the BREQ or HOLD outputs
from the potential masters and to assign the bus to the requestor. A priority scheme
must be included to handle cases where more than one device is requesting the bus.
The arbitration logic must assert HOLD to the device that must relinquish the bus. Once
HLDA is asserted by all of these devices, the arbitration logic may assert HLDA or
BACK# to the device requesting the bus. The requestor remains the bus master until
another device needs the bus.
These two arbitration techniques can be combined to create a more elaborate
arbitration scheme that is driven by a device that needs the bus but guarantees that
every device gets time on the bus. It is important that an arbitration scheme be
selected to best fit the needs of each system's implementation.
Intel® Quark
Core
DMA
MEM
I/O
Arbitration
Logic
ACQ
ACK
HLDA 0
HOLD 0
DRQ
DACK
Address Bus
Data Bus
Control Bus
BDCK
BREQ